?? coregen.log
字號(hào):
# Xilinx CORE Generator 6.3.03i
# User = Administrator
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in D:\treasure\work\sericommu\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=D:\treasure\work\sericommu
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=D:\treasure\work\sericommu
SETPROJECT .
Set current Project to D:\treasure\work\sericommu
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1204
XIPCPJSENDCORES spartan2
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