begin
	O <= ( I0 and I1 and I2 and I3 );
end Eval;

library IEEE;
use IEEE.std_logic_1164.all;

entity OR6 is
	port ( 
		O : out std_logic ;
		I5 : in std_logic ;
		I4 : in std_logic ;
		I3 : in std_logic ;
		I2 : in std_logic ;
		I1 : in std_logic ;
		I0 : in std_logic );
end OR6 ;

architecture Eval of OR6 is
	
begin
	O <= not ( ( not I0 ) and ( not I1 ) and ( not I2 ) and ( not I3 ) 
	and ( not I4 ) and ( not I5 ) );
end Eval;

library IEEE;
use IEEE.std_logic_1164.all;

entity OR8 is
	port ( 
		O : out std_logic ;
		I7 : in std_logic ;
		I6 : in std_logic ;
		I5 : in std_logic ;
		I4 : in std_logic ;
		I3 : in std_logic ;
		I2 : in std_logic ;
		I1 : in std_logic ;
		I0 : in std_logic );
end OR8 ;

architecture Eval of OR8 is
	
begin
	O <= not ( ( not I0 ) and ( not I1 ) and ( not I2 ) and ( not I3 ) 
	and ( not I4 ) and ( not I5 ) and ( not I6 ) and ( not I7 ) );
end Eval;

library IEEE;
use IEEE.std_logic_1164.all;

entity AND7 is
	port ( 
		O : out std_logic ;
		I6 : in std_logic ;
		I5 : in std_logic ;
		I4 : in std_logic ;
		I3 : in std_logic ;
		I2 : in std_logic ;
		I1 : in std_logic ;
		I0 : in std_logic );
end AND7 ;

architecture Eval of AND7 is
	
begin
	O <= ( I0 and I1 and I2 and I3 and I4 and I5 and I6 );
end Eval;

library IEEE;
use IEEE.std_logic_1164.all;

entity OR7 is
	port ( 
		O : out std_logic ;
		I6 : in std_logic ;
		I5 : in std_logic ;
		I4 : in std_logic ;
		I3 : in std_logic ;
		I2 : in std_logic ;
		I1 : in std_logic ;
		I0 : in std_logic );
end OR7 ;

architecture Eval of OR7 is
	
begin
	O <= not ( ( not I0 ) and ( not I1 ) and ( not I2 ) and ( not I3 ) 
	and ( not I4 ) and ( not I5 ) and ( not I6 ) );
end Eval;

library IEEE;
use IEEE.std_logic_1164.all;

entity AND6 is
	port ( 
		O : out std_logic ;
		I5 : in std_logic ;
		I4 : in std_logic ;
		I3 : in std_logic ;
		I2 : in std_logic ;
		I1 : in std_logic ;
		I0 : in std_logic );
end AND6 ;

architecture Eval of AND6 is
	
begin
	O <= ( I0 and I1 and I2 and I3 and I4 and I5 );
end Eval;

library IEEE;
use IEEE.std_logic_1164.all;

entity AND8 is
	port ( 
		O : out std_logic ;
		I7 : in std_logic ;
		I6 : in std_logic ;
		I5 : in std_logic ;
		I4 : in std_logic ;
		I3 : in std_logic ;
		I2 : in std_logic ;
		I1 : in std_logic ;
		I0 : in std_logic );
end AND8 ;

architecture Eval of AND8 is
	
begin
	O <= ( I0 and I1 and I2 and I3 and I4 and I5 and I6 and I7 );
end Eval;

library IEEE;
use IEEE.std_logic_1164.all;

entity usbEP0 is
	generic(
		epin_mask : bit_vector(3 downto 0) := "0001";
		episo_mask : bit_vector(3 downto 0) := "0000";
		epout_mask : bit_vector(3 downto 0) := "0001";
		epsetup_mask : bit_vector(3 downto 0) := "0001"
		);
	port ( 
		clk12 : in std_logic ;
		clk48 : in std_logic ;
		rst : in std_logic ;
		uc_wradx : in std_logic ;
		uc_wrctrl : in std_logic ;
		uc_wren : in std_logic ;
		urx0 : in std_logic ;
		urxd : in std_logic ;
		datain : in std_logic_vector (3 downto 1) ;
		nak : in std_logic_vector (3 downto 1) ;
		stall : in std_logic_vector (3 downto 1) ;
		togglein : in std_logic_vector (3 downto 1) ;
		txd : in std_logic_vector (7 downto 0) ;
		uc_adx : in std_logic_vector (2 downto 0) ;
		uc_ctrl : in std_logic_vector (7 downto 0) ;
		uc_dadx : in std_logic_vector (6 downto 0) ;
		uc_dwr : in std_logic_vector (7 downto 0) ;
		clk12o : out std_logic ;
		rxen : out std_logic ;
		sof_trac : out std_logic ;
		txen : out std_logic ;
		utx0 : out std_logic ;
		utxd : out std_logic ;
		utxoe : out std_logic ;
		in_trac : out std_logic_vector (3 downto 0) ;
		out_trac : out std_logic_vector (3 downto 0) ;
		rxd : out std_logic_vector (7 downto 0) ;
		rxfrm : out std_logic_vector (10 downto 0) ;
		setup_trac : out std_logic_vector (3 downto 0) ;
		uc_drd : out std_logic_vector (7 downto 0) ;
		uc_status : out std_logic_vector (7 downto 0) );
end usbEP0 ;

architecture Eval of usbEP0 is
	
	component lbx16x8
		port ( 
			A : in std_logic_vector (3 downto 0) ;
			DI : in std_logic_vector (7 downto 0) ;
			WR_EN : in std_logic ;
			WR_CLK : in std_logic ;
			DO : out std_logic_vector (7 downto 0) );
	end component;
	
	component DFF_CLR_PRE
		port ( 
			D : in std_logic ;
			C : in std_logic ;
			CLR : in std_logic ;
			PRE : in std_logic ;
			Q : out std_logic );
	end component;
	
	component DFF_CLR_Cb_PRE
		port ( 
			D : in std_logic ;
			C : in std_logic ;
			CLR : in std_logic ;
			PRE : in std_logic ;
			Q : out std_logic );
	end component;
	
	component TBUF
		port ( 
			O : out std_logic ;
			I : in std_logic ;
			T : in std_logic );
	end component;
	
	component AND2
		port ( 
			O : out std_logic ;
			I1 : in std_logic ;
			I0 : in std_logic );
	end component;
	
	component OR2
		port ( 
			O : out std_logic ;
			I1 : in std_logic ;
			I0 : in std_logic );
	end component;
	
	component INV
		port ( 
			O : out std_logic ;
			I : in std_logic );
	end component;
	
	component AND3
		port ( 
			O : out std_logic ;
			I2 : in std_logic ;
			I1 : in std_logic ;
			I0 : in std_logic );
	end component;
	
	component XOR2
		port ( 
			O : out std_logic ;
			I1 : in std_logic ;
			I0 : in std_logic );
	end component;
	
	component OR4
		port ( 
			O : out std_logic ;
			I3 : in std_logic ;
			I2 : in std_logic ;
			I1 : in std_logic ;
			I0 : in std_logic );
	end component;
	
	component OR3
		port ( 
			O : out std_logic ;
			I2 : in std_logic ;
			I1 : in std_logic ;
			I0 : in std_logic );
	end component;
	
	component AND5
		port ( 
			O : out std_logic ;
			I4 : in std_logic ;
			I3 : in std_logic ;
			I2 : in std_logic ;
			I1 : in std_logic ;
			I0 : in std_logic );
	end component;
	
	component OR5
		port ( 
			O : out std_logic ;
			I4 : in std_logic ;
			I3 : in std_logic ;
			I2 : in std_logic ;
			I1 : in std_logic ;
			I0 : in std_logic );
	end component;
	
	component AND4
		port ( 
			O : out std_logic ;
			I3 : in std_logic ;
			I2 : in std_logic ;
			I1 : in std_logic ;
			I0 : in std_logic );
	end component;
	
	component OR6
		port ( 
			O : out std_logic ;
			I5 : in std_logic ;
			I4 : in std_logic ;
			I3 : in std_logic ;
			I2 : in std_logic ;
			I1 : in std_logic ;
			I0 : in std_logic );
	end component;