--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--     
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--     
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--     
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--------------------------------------------------------------------------------
-- Project:      Full-Speed USB 1.1 Function Controller
-- File:         xspUC.vhd
-- Description:  XSP-010 board, 8051 port 0 demux.
-- Version:      FB, 2000jul29
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity xspUC is
	port(
		-- 8051 signals
		signal ALE:  in    STD_LOGIC;
		signal P0:   inout STD_LOGIC_VECTOR(7 downto 0);
		signal P2:   in    STD_LOGIC_VECTOR(7 downto 0);
		signal PSEN: in    STD_LOGIC;
		signal RD:   in    STD_LOGIC;
		-- SRAM signals
		signal A:    out   STD_LOGIC_VECTOR(15 downto 0);
		signal OE:   out   STD_LOGIC;
		signal DOUT: in    STD_LOGIC_VECTOR(7 downto 0);
		signal CE:   out   STD_LOGIC;
		signal DDRV: in    STD_LOGIC
		);
end xspUC;

--------------------------------------------------------------------------------
architecture BHV of xspUC is
	signal alatch: STD_LOGIC_VECTOR(7 downto 0);
	signal aii: STD_LOGIC_VECTOR(15 downto 0);
begin
	process(ALE) --, P0)
	begin
		if falling_edge(ALE) then
			alatch<= P0;
		end if;
	end process;
	
	aii <= P2 & alatch;
	a   <= Aii;
	P0<= DOUT when DDRV= '1' else (others=> 'Z');
	CE<= aii(15);
	OE<= PSEN and RD;
	
end BHV;

--------------------------------------------------------------------------------
-- end of file