library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity coder16_4 is
port(a:in std_logic_vector(15 downto 0);
     z:out std_logic_vector(3 downto 0));
end coder16_4 ;
architecture rtl of coder16_4 is
signal s_tmp,ys_tmp,yex_tmp,ys_tmp1,yex_tmp1:std_logic;
signal b,c:std_logic_vector(7 downto 0);
signal d,e:std_logic_vector(2 downto 0);
component sn74ls148
port(i:in std_logic_vector(7 downto 0);
	s:in std_logic;
	ys,yex:out std_logic;
	y:out std_logic_vector(2 downto 0));
END COMPONENT;
begin 
s_tmp<='0';
b<=a(7)&a(6)&a(5)&a(4)&a(3)&a(2)&a(1)&a(0);
c<=a(15)&a(14)&a(13)&a(12)&a(11)&a(10)&a(9)&a(8);
u1:sn74ls148 port map(b,s_tmp,ys_tmp,yex_tmp,d);
u2:sn74ls148 port map(c,ys_tmp,ys_tmp1,yex_tmp1,e);
z(3)<=not ys_tmp;
z(2)<=not(d(2) AND e(2));
z(1)<=not(d(1) AND e(1));
z(0)<=not(d(0) AND e(0));
end rtl;