library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bsr is
port(din :in std_logic_vector(7 downto 0);
	s:in std_logic_vector(2 downto 0);
	clk,enb:in std_logic;
	wr:out std_logic;
	dout:out std_logic_vector(7 downto 0));
end bsr;
architecture behav of bsr is  
signal counter:integer;
begin 
	process(clk)
		variable sc:integer;
		variable tmp,tmp1:std_logic;
		begin
		if(clk'event and clk='1')then
			
			if(enb='0')then
				counter<=0;
				wr<='1';
			elsif(counter<sc)then
				sc:=conv_integer(s);
				dout(0)<=din(7);
				for i in 7 downto 1 loop
				dout(i)<=din(i-1);
				end loop;
				counter<=counter+1;
				wr<='1';
			else
				wr<='0';
			end if;
		end if;
	end process;
end behav;