library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter_1m is
port(clk,updn,bcdwr:in std_logic;
	d,e:out std_logic_vector(9 downto 0);
	c:out std_logic);
end counter_1m;
architecture rtl of counter_1m is
signal clr,en,c_tmp:std_logic;
signal a:std_logic_vector(9 downto 0);
component counter_1024 
port(clk,clr,en,updn,bcdwr:in std_logic;
            datain:in std_logic_vector(9 downto 0);
			c:out std_logic;
            q:out std_logic_vector (9 downto 0));
end component;
begin 
a<="0000000000";
clr<='0';
en<='1';
u1:counter_1024 port map(clk,clr,en,updn,bcdwr,a,c_tmp,d);
u2:counter_1024 port map(c_tmp,clr ,en,updn ,bcdwr,a,c,e);
end rtl;