library ieee;
use ieee.std_logic_1164.all;
entity shift8 is
	port(a,clk1,clr1:in std_logic;
			b:out std_logic);
end shift8;
architecture rtl of shift8 is
component dff4
port(clk,clr,d:in std_logic;
				q:out std_logic);
end component;
signal z:std_logic_vector(0 to 8);
begin
z(0)<=a;
g1:for i in 0 to 7 generate
difx:dff4 port map(clk1,clr1,z(i),z(i+1));
end generate;
b<=z(8);
end rtl;