`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:57:35 04/23/2005
// Design Name:   led_top2
// Module Name:   E:\demo\seg_led\rtl\led_top2_tb.v
// Project Name:  SP3400
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: led_top2
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module led_top3_tb_v;

	// Inputs
	reg clk;
	reg rst_n;

	// Outputs
	wire [11:0] seg;

	// Instantiate the Unit Under Test (UUT)
	led_top3 uut (
		.seg(seg), 
		.clk(clk), 
		.rst_n(rst_n)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		rst_n = 0;

		// Wait 100 ns for global reset to finish
		#100;
        rst_n = 1'b1;
		// Add stimulus here

	end

always #20 clk=~clk;
      
endmodule