Project Information                            c:\maxplus2\files\send\send.rpt

MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 12/04/2002 17:24:31

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

send      EPM7128SLC84-10  10       1        0      65      25          50 %

User Pins:                 10       1        0  



Project Information                            c:\maxplus2\files\send\send.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'clock' chosen for auto global Clock


Project Information                            c:\maxplus2\files\send\send.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

send@83                           clock
send@56                           key_send0
send@57                           key_send1
send@58                           key_send2
send@60                           key_send3
send@61                           key_send4
send@63                           key_send5
send@64                           key_send6
send@65                           key_send7
send@2                            key_start
send@5                            txd


Project Information                            c:\maxplus2\files\send\send.rpt

** FILE HIERARCHY **



|lpm_add_sub:550|
|lpm_add_sub:550|addcore:adder|
|lpm_add_sub:550|addcore:adder|addcore:adder1|
|lpm_add_sub:550|addcore:adder|addcore:adder0|
|lpm_add_sub:550|altshift:result_ext_latency_ffs|
|lpm_add_sub:550|altshift:carry_ext_latency_ffs|
|lpm_add_sub:550|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:551|
|lpm_add_sub:551|addcore:adder|
|lpm_add_sub:551|addcore:adder|addcore:adder0|
|lpm_add_sub:551|altshift:result_ext_latency_ffs|
|lpm_add_sub:551|altshift:carry_ext_latency_ffs|
|lpm_add_sub:551|altshift:oflow_ext_latency_ffs|


Device-Specific Information:                   c:\maxplus2\files\send\send.rpt
send

***** Logic for device 'send' compiled without errors.




Device: EPM7128SLC84-10

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    Enable JTAG Support                        = ON
    User Code                                  = ffff
    MultiVolt I/O                              = OFF

                                          k                                   
               R  R  R  R     R     R     e              R  R  R     R  R  R  
               E  E  E  E     E     E     y              E  E  E     E  E  E  
               S  S  S  S     S     S  V  _              S  S  S     S  S  S  
               E  E  E  E     E     E  C  s        c     E  E  E  V  E  E  E  
               R  R  R  R     R     R  C  t        l     R  R  R  C  R  R  R  
               V  V  V  V  G  V  t  V  I  a  G  G  o  G  V  V  V  C  V  V  V  
               E  E  E  E  N  E  x  E  N  r  N  N  c  N  E  E  E  I  E  E  E  
               D  D  D  D  D  D  d  D  T  t  D  D  k  D  D  D  D  O  D  D  D  
             -----------------------------------------------------------------_ 
           /  11 10  9  8  7  6  5  4  3  2  1 84 83 82 81 80 79 78 77 76 75   | 
 RESERVED | 12                                                              74 | RESERVED 
    VCCIO | 13                                                              73 | RESERVED 
     #TDI | 14                                                              72 | GND 
 RESERVED | 15                                                              71 | #TDO 
 RESERVED | 16                                                              70 | RESERVED 
 RESERVED | 17                                                              69 | RESERVED 
 RESERVED | 18                                                              68 | RESERVED 
      GND | 19                                                              67 | RESERVED 
 RESERVED | 20                                                              66 | VCCIO 
 RESERVED | 21                                                              65 | key_send7 
 RESERVED | 22                       EPM7128SLC84-10                        64 | key_send6 
     #TMS | 23                                                              63 | key_send5 
 RESERVED | 24                                                              62 | #TCK 
 RESERVED | 25                                                              61 | key_send4 
    VCCIO | 26                                                              60 | key_send3 
 RESERVED | 27                                                              59 | GND 
 RESERVED | 28                                                              58 | key_send2 
 RESERVED | 29                                                              57 | key_send1 
 RESERVED | 30                                                              56 | key_send0 
 RESERVED | 31                                                              55 | RESERVED 
      GND | 32                                                              54 | RESERVED 
          |_  33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  _| 
            ------------------------------------------------------------------ 
               R  R  R  R  R  V  R  R  R  G  V  R  R  R  G  R  R  R  R  R  V  
               E  E  E  E  E  C  E  E  E  N  C  E  E  E  N  E  E  E  E  E  C  
               S  S  S  S  S  C  S  S  S  D  C  S  S  S  D  S  S  S  S  S  C  
               E  E  E  E  E  I  E  E  E     I  E  E  E     E  E  E  E  E  I  
               R  R  R  R  R  O  R  R  R     N  R  R  R     R  R  R  R  R  O  
               V  V  V  V  V     V  V  V     T  V  V  V     V  V  V  V  V     
               E  E  E  E  E     E  E  E        E  E  E     E  E  E  E  E     
               D  D  D  D  D     D  D  D        D  D  D     D  D  D  D  D     
                                                                              


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:                   c:\maxplus2\files\send\send.rpt
send

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16    16/16(100%)   1/ 8( 12%)  11/16( 68%)  27/36( 75%) 
B:    LC17 - LC32     0/16(  0%)   1/ 8( 12%)   0/16(  0%)   0/36(  0%) 
C:    LC33 - LC48     0/16(  0%)   1/ 8( 12%)   0/16(  0%)   0/36(  0%) 
D:    LC49 - LC64     0/16(  0%)   0/ 8(  0%)   0/16(  0%)   0/36(  0%) 
E:    LC65 - LC80     1/16(  6%)   0/ 8(  0%)   0/16(  0%)   2/36(  5%) 
F:    LC81 - LC96    16/16(100%)   6/ 8( 75%)   0/16(  0%)  16/36( 44%) 
G:   LC97 - LC112    16/16(100%)   4/ 8( 50%)   6/16( 37%)  32/36( 88%) 
H:  LC113 - LC128    16/16(100%)   0/ 8(  0%)  10/16( 62%)  36/36(100%) 


Total dedicated input pins used:                 2/4      ( 50%)
Total I/O pins used:                            13/64     ( 20%)
Total logic cells used:                         65/128    ( 50%)
Total shareable expanders used:                 25/128    ( 19%)
Total Turbo logic cells used:                   65/128    ( 50%)
Total shareable expanders not available (n/a):   2/128    (  1%)
Average fan-in:                                  6.32
Total fan-in:                                   411

Total input pins required:                      10
Total fast input logic cells required:           0
Total output pins required:                      1
Total bidirectional pins required:               0
Total reserved pins required                     4
Total logic cells required:                     65
Total flipflops required:                       17
Total product terms required:                  203
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:          23

Synthesized logic cells:                        37/ 128   ( 28%)



Device-Specific Information:                   c:\maxplus2\files\send\send.rpt
send

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  83      -   -       INPUT  G            0      0   0    0    0    0    0  clock
  56   (86)  (F)      INPUT               0      0   0    0    0    1    5  key_send0
  57   (88)  (F)      INPUT               0      0   0    0    0    1    5  key_send1
  58   (91)  (F)      INPUT               0      0   0    0    0    1    5  key_send2
  60   (93)  (F)      INPUT               0      0   0    0    0    1    5  key_send3
  61   (94)  (F)      INPUT               0      0   0    0    0    1    5  key_send4
  63   (97)  (G)      INPUT               0      0   0    0    0    1    5  key_send5
  64   (99)  (G)      INPUT               0      0   0    0    0    1    5  key_send6
  65  (101)  (G)      INPUT               0      0   0    0    0    1    5  key_send7
   2      -   -       INPUT               0      0   0    0    0    0   18  key_start


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:                   c:\maxplus2\files\send\send.rpt
send

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   5     14    A         FF      t        8      8   0    8    4    1    0  txd (:547)


Code: