?? receice.rpt
字號:
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\maxplus2\files\receive\receice.rpt
receice
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
30 37 C FF t ! 0 0 0 0 8 1 1 sbuf0 (:393)
31 35 C FF t ! 0 0 0 0 8 2 0 sbuf1 (:392)
33 64 D FF t ! 0 0 0 0 8 2 0 sbuf2 (:391)
34 61 D FF t ! 0 0 0 0 8 2 0 sbuf3 (:390)
35 59 D FF t ! 0 0 0 0 8 2 0 sbuf4 (:389)
36 57 D FF t ! 0 0 0 0 8 2 0 sbuf5 (:388)
37 56 D FF t ! 0 0 0 0 8 2 0 sbuf6 (:387)
39 53 D FF t ! 0 0 0 0 8 2 0 sbuf7 (:386)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\maxplus2\files\receive\receice.rpt
receice
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 50 D SOFT t 0 0 0 0 2 0 1 |lpm_add_sub:411|addcore:adder|addcore:adder0|result_node1
- 54 D SOFT t 0 0 0 0 3 0 1 |lpm_add_sub:411|addcore:adder|addcore:adder0|result_node2
- 55 D SOFT t 0 0 0 0 4 0 1 |lpm_add_sub:411|addcore:adder|addcore:adder0|result_node3
(77) 123 H SOFT t 0 0 0 0 5 0 1 |lpm_add_sub:411|addcore:adder|addcore:adder0|result_node4
- 119 H SOFT t 0 0 0 0 6 0 1 |lpm_add_sub:411|addcore:adder|addcore:adder0|result_node5
(73) 115 H SOFT t 0 0 0 0 7 0 1 |lpm_add_sub:411|addcore:adder|addcore:adder0|result_node6
(41) 49 D SOFT t 0 0 0 0 2 0 10 |lpm_add_sub:412|addcore:adder|addcore:adder0|result_node1
(40) 51 D SOFT t 0 0 0 0 3 0 5 |lpm_add_sub:412|addcore:adder|addcore:adder0|result_node2
- 52 D SOFT t 0 0 0 0 4 0 10 |lpm_add_sub:412|addcore:adder|addcore:adder0|result_node3
- 47 C SOFT t 0 0 0 0 2 0 2 |lpm_add_sub:413|addcore:adder|addcore:adder0|result_node1
- 34 C SOFT t 0 0 0 0 3 0 2 |lpm_add_sub:413|addcore:adder|addcore:adder0|result_node2
(25) 45 C SOFT t 0 0 0 0 4 0 2 |lpm_add_sub:413|addcore:adder|addcore:adder0|result_node3
- 124 H TFFE + t 0 0 0 0 5 0 9 clock_div6 (:61)
- 114 H DFFE + t 0 0 0 0 5 0 10 clock_div5 (:62)
(81) 128 H DFFE + t 0 0 0 0 5 0 11 clock_div4 (:63)
(80) 126 H DFFE + t 0 0 0 0 5 0 12 clock_div3 (:64)
- 127 H DFFE + t 0 0 0 0 5 0 5 clock_div2 (:65)
(79) 125 H DFFE + t 0 0 0 0 5 0 6 clock_div1 (:66)
- 121 H DFFE + t 0 0 0 0 5 0 7 clock_div0 (:67)
- 113 H DFFE + t 0 0 0 0 4 8 12 clock_pluse (:71)
- 33 C DFFE t 1 0 1 1 6 8 14 count_reg3 (:105)
- 36 C TFFE t 0 0 0 1 6 8 15 count_reg2 (:106)
(28) 40 C DFFE t 1 0 1 1 6 8 16 count_reg1 (:107)
- 41 C TFFE t 0 0 0 1 6 8 14 count_reg0 (:108)
(24) 46 C TFFE t 0 0 0 1 12 0 3 bit_cnt3 (:167)
- 44 C TFFE t 0 0 0 1 11 0 5 bit_cnt2 (:168)
- 42 C TFFE t 0 0 0 1 10 0 7 bit_cnt1 (:169)
- 39 C TFFE t 0 0 0 1 9 0 8 bit_cnt0 (:170)
- 62 D TFFE t 1 1 0 1 10 0 2 bit_collect1 (:252)
- 60 D TFFE t 1 1 0 1 10 0 2 bit_collect0 (:253)
(29) 38 C SOFT s t 1 0 1 0 11 0 1 ~321~1
(27) 43 C DFFE t 13 0 1 1 18 8 13 rxd_start_reg (:322)
- 58 D TFFE t 4 1 1 1 12 1 1 uart_buf9 (:385)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\maxplus2\files\receive\receice.rpt
receice
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------------------- LC47 |lpm_add_sub:413|addcore:adder|addcore:adder0|result_node1
| +--------------------------- LC34 |lpm_add_sub:413|addcore:adder|addcore:adder0|result_node2
| | +------------------------- LC45 |lpm_add_sub:413|addcore:adder|addcore:adder0|result_node3
| | | +----------------------- LC37 sbuf0
| | | | +--------------------- LC35 sbuf1
| | | | | +------------------- LC33 count_reg3
| | | | | | +----------------- LC36 count_reg2
| | | | | | | +--------------- LC40 count_reg1
| | | | | | | | +------------- LC41 count_reg0
| | | | | | | | | +----------- LC46 bit_cnt3
| | | | | | | | | | +--------- LC44 bit_cnt2
| | | | | | | | | | | +------- LC42 bit_cnt1
| | | | | | | | | | | | +----- LC39 bit_cnt0
| | | | | | | | | | | | | +--- LC38 ~321~1
| | | | | | | | | | | | | | +- LC43 rxd_start_reg
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'C':
LC47 -> - - - - - - - - - - - - - * * | - - * - - - - - | <-- |lpm_add_sub:413|addcore:adder|addcore:adder0|result_node1
LC34 -> - - - - - - - - - - - - - * * | - - * - - - - - | <-- |lpm_add_sub:413|addcore:adder|addcore:adder0|result_node2
LC45 -> - - - - - - - - - - - - - * * | - - * - - - - - | <-- |lpm_add_sub:413|addcore:adder|addcore:adder0|result_node3
LC37 -> - - - * - - - - - - - - - - * | - - * - - - - - | <-- sbuf0
LC35 -> - - - * * - - - - - - - - - - | - - * - - - - - | <-- sbuf1
LC33 -> - - - * * * * * * * * * * * * | - - * * - - - - | <-- count_reg3
LC36 -> - - - * * * * * * * * * * * * | - - * * - - - - | <-- count_reg2
LC40 -> - - - * * * * * * * * * * * * | - - * * - - - - | <-- count_reg1
LC41 -> - - - * * - * - * * * * * * * | - - * * - - - - | <-- count_reg0
LC46 -> - - * - - - - - - * - - - - * | - - * - - - - - | <-- bit_cnt3
LC44 -> - * * - - - - - - * * - - - * | - - * - - - - - | <-- bit_cnt2
LC42 -> * * * - - - - - - * * * - - * | - - * - - - - - | <-- bit_cnt1
LC39 -> * * * - - - - - - * * * * - * | - - * - - - - - | <-- bit_cnt0
LC38 -> - - - - - - - - - - - - - - * | - - * - - - - - | <-- ~321~1
LC43 -> - - - * * * * * * * * * * * * | - - * * - - - - | <-- rxd_start_reg
Pin
83 -> - - - - - - - - - - - - - - - | - - - - - - - - | <-- clock
4 -> - - - - - * * * * * * * * - * | - - * * - - - - | <-- rxd
LC49 -> - - - - - - - * - * * * * * * | - - * * - - - - | <-- |lpm_add_sub:412|addcore:adder|addcore:adder0|result_node1
LC51 -> - - - - - - - - - - - - - * * | - - * * - - - - | <-- |lpm_add_sub:412|addcore:adder|addcore:adder0|result_node2
LC52 -> - - - - - * - - - * * * * * * | - - * * - - - - | <-- |lpm_add_sub:412|addcore:adder|addcore:adder0|result_node3
LC64 -> - - - - * - - - - - - - - - - | - - * * - - - - | <-- sbuf2
LC113-> - - - * * * * * * * * * * - * | - - * * - - - - | <-- clock_pluse
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\maxplus2\files\receive\receice.rpt
receice
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+----------------------------- LC50 |lpm_add_sub:411|addcore:adder|addcore:adder0|result_node1
| +--------------------------- LC54 |lpm_add_sub:411|addcore:adder|addcore:adder0|result_node2
| | +------------------------- LC55 |lpm_add_sub:411|addcore:adder|addcore:adder0|result_node3
| | | +----------------------- LC49 |lpm_add_sub:412|addcore:adder|addcore:adder0|result_node1
| | | | +--------------------- LC51 |lpm_add_sub:412|addcore:adder|addcore:adder0|result_node2
| | | | | +------------------- LC52 |lpm_add_sub:412|addcore:adder|addcore:adder0|result_node3
| | | | | | +----------------- LC64 sbuf2
| | | | | | | +--------------- LC61 sbuf3
| | | | | | | | +------------- LC59 sbuf4
| | | | | | | | | +----------- LC57 sbuf5
| | | | | | | | | | +--------- LC56 sbuf6
| | | | | | | | | | | +------- LC53 sbuf7
| | | | | | | | | | | | +----- LC62 bit_collect1
| | | | | | | | | | | | | +--- LC60 bit_collect0
| | | | | | | | | | | | | | +- LC58 uart_buf9
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'D':
LC49 -> - - - - - - - - - - - - * * * | - - * * - - - - | <-- |lpm_add_sub:412|addcore:adder|addcore:adder0|result_node1
LC51 -> - - - - - - - - - - - - * * * | - - * * - - - - | <-- |lpm_add_sub:412|addcore:adder|addcore:adder0|result_node2
LC52 -> - - - - - - - - - - - - * * * | - - * * - - - - | <-- |lpm_add_sub:412|addcore:adder|addcore:adder0|result_node3
LC64 -> - - - - - - * - - - - - - - - | - - * * - - - - | <-- sbuf2
LC61 -> - - - - - - * * - - - - - - - | - - - * - - - - | <-- sbuf3
LC59 -> - - - - - - - * * - - - - - - | - - - * - - - - | <-- sbuf4
LC57 -> - - - - - - - - * * - - - - - | - - - * - - - - | <-- sbuf5
LC56 -> - - - - - - - - - * * - - - - | - - - * - - - - | <-- sbuf6
LC53 -> - - - - - - - - - - * * - - - | - - - * - - - - | <-- sbuf7
LC62 -> - - - - - - - - - - - - * - * | - - - * - - - - | <-- bit_collect1
LC60 -> - - - - - - - - - - - - - * * | - - - * - - - - | <-- bit_collect0
LC58 -> - - - - - - - - - - - * - - * | - - - * - - - - | <-- uart_buf9
Pin
83 -> - - - - - - - - - - - - - - - | - - - - - - - - | <-- clock
4 -> - - - - - - - - - - - - * * * | - - * * - - - - | <-- rxd
LC126-> - - * - - - - - - - - - - - - | - - - * - - - * | <-- clock_div3
LC127-> - * * - - - - - - - - - - - - | - - - * - - - * | <-- clock_div2
LC125-> * * * - - - - - - - - - - - - | - - - * - - - * | <-- clock_div1
LC121-> * * * - - - - - - - - - - - - | - - - * - - - * | <-- clock_div0
LC113-> - - - - - - * * * * * * * * * | - - * * - - - - | <-- clock_pluse
LC33 -> - - - - - * * * * * * * * * * | - - * * - - - - | <-- count_reg3
LC36 -> - - - - * * * * * * * * * * * | - - * * - - - - | <-- count_reg2
LC40 -> - - - * * * * * * * * * * * * | - - * * - - - - | <-- count_reg1
LC41 -> - - - * * * * * * * * * * * * | - - * * - - - - | <-- count_reg0
LC43 -> - - - - - - * * * * * * * * * | - - * * - - - - | <-- rxd_start_reg
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\maxplus2\files\receive\receice.rpt
receice
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+--------------------- LC123 |lpm_add_sub:411|addcore:adder|addcore:adder0|result_node4
| +------------------- LC119 |lpm_add_sub:411|addcore:adder|addcore:adder0|result_node5
| | +----------------- LC115 |lpm_add_sub:411|addcore:adder|addcore:adder0|result_node6
| | | +--------------- LC124 clock_div6
| | | | +------------- LC114 clock_div5
| | | | | +----------- LC128 clock_div4
| | | | | | +--------- LC126 clock_div3
| | | | | | | +------- LC127 clock_div2
| | | | | | | | +----- LC125 clock_div1
| | | | | | | | | +--- LC121 clock_div0
| | | | | | | | | | +- LC113 clock_pluse
| | | | | | | | | | |
| | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC123-> - - - - - * - - - - - | - - - - - - - * | <-- |lpm_add_sub:411|addcore:adder|addcore:adder0|result_node4
LC119-> - - - - * - - - - - - | - - - - - - - * | <-- |lpm_add_sub:411|addcore:adder|addcore:adder0|result_node5
LC115-> - - - * - - - - - - - | - - - - - - - * | <-- |lpm_add_sub:411|addcore:adder|addcore:adder0|result_node6
LC124-> - - * * * * * * * * * | - - - - - - - * | <-- clock_div6
LC114-> - * * * * * * * * * * | - - - - - - - * | <-- clock_div5
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