module receice(rxd,clock,sbuf);
	//9600BPS,8位數(shù)據(jù),1位停止位
   input rxd;
	input clock;
	output [7:0] sbuf;

	reg [3:0] count_reg;				//RXD數(shù)據(jù)狀態(tài)計(jì)數(shù)器
	reg [9:0] uart_buf;				//串行數(shù)據(jù)接收緩沖區(qū)
	reg [3:0] bit_cnt;				//串行數(shù)據(jù)當(dāng)前位計(jì)數(shù)
	reg [2:0] bit_collect;			//采集數(shù)據(jù)緩沖區(qū)
	reg [6:0] clock_div;				//波特率時(shí)鐘分頻:9600*16=11.0592/72
	reg clock_pluse;					//狀態(tài)計(jì)數(shù)器開(kāi)始標(biāo)志
	reg rxd_start_reg;				//串行接收開(kāi)始標(biāo)志
	reg rxd_end;						//串行接收接收標(biāo)志
	reg rxd_dat;

//時(shí)鐘分頻,產(chǎn)生一個(gè)9600*16的頻率
always @(negedge clock)
begin
	if (clock_div<7'd72)
	begin
		clock_div=clock_div+1;
		clock_pluse=0;
	end
	else
	begin
		clock_div=0;
		clock_pluse=1;
	end
end

//接收解碼
always @(posedge clock_pluse)
begin
	if (rxd_start_reg==1'b0)
	begin
		//檢測(cè)開(kāi)始位
		if (rxd==1'b0)
		begin
			rxd_start_reg=1'b1;
			count_reg=4'h0;
			bit_cnt=4'h0;
		end
	end
	else
	begin
		//接收狀態(tài)頻率微調(diào)
		if (count_reg < 4'he)
			count_reg=count_reg+1;
		else
			count_reg=0;
	
		if (count_reg==4'h6)					//數(shù)據(jù)采集
			bit_collect[0]=rxd;
		if (count_reg==4'h7)
			bit_collect[1]=rxd;

		if (count_reg==4'h8)
		begin
			bit_collect[2]=rxd;
			rxd_dat=(bit_collect[0] & bit_collect[1]) | (bit_collect[1] & bit_collect[2]) | (bit_collect[0] & bit_collect[2]);
			uart_buf=uart_buf>>1;
			uart_buf[9]=rxd_dat;
			bit_cnt=bit_cnt+1;
			if (bit_cnt==4'h1 && uart_buf[0]==1'b1)
			begin
				rxd_start_reg=0;
			end
		end

		//檢測(cè)接收結(jié)束
		if (bit_cnt > 4'h9)
		begin
			rxd_end=1;
			rxd_start_reg=0;
		end

	end
end

assign sbuf=~uart_buf[8:1];
endmodule