Release 4.1WP1.x - xst E.31Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to .CPU : 0.00 / 0.08 s | Elapsed : 0.00 / 0.00 s --> Parameter overwrite set to YESCPU : 0.00 / 0.08 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.08 s | Elapsed : 0.00 / 0.00 s --> =========================================================================---- Source ParametersInput Format                       : VHDLInput File Name                    : main_bcd.prj---- Target ParametersTarget Device                      : XC9500XLOutput File Name                   : main_bcdOutput Format                      : NGCTarget Technology                  : 9500xl---- Source OptionsEntity Name                        : main_bcdAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Flip-Flop Type                 : DMux Extraction                     : YESResource Sharing                   : YESComplex Clock Enable Extraction    : YES---- Target OptionsAdd IO Buffers                     : YESEquivalent register Removal        : YESMacro Generator                    : AutoMACRO Preserve                     : YESXOR Preserve                       : YES---- General OptionsOptimization Criterion             : SpeedOptimization Effort                : 1Check Attribute Syntax             : YESKeep Hierarchy                     : YES---- Other OptionsClock Enable                       : YESwysiwyg                            : NO=========================================================================Compiling vhdl file F:/CPLD_BOARD/d_BCD/d_BCD.vhd in Library work.Entity <d_bcd> (Architecture <behavioral>) compiled.Compiling vhdl file F:/CPLD_BOARD/d_BCD/main_bcd.vhd in Library work.Entity <main_bcd> (Architecture <behavioral>) compiled.Analyzing Entity <main_bcd> (Architecture <Behavioral>).Entity <main_bcd> analyzed. Unit <main_bcd> generated.Analyzing Entity <d_bcd> (Architecture <behavioral>).Entity <d_bcd> analyzed. Unit <d_bcd> generated.Synthesizing Unit <d_bcd>.    Related source file is F:/CPLD_BOARD/d_BCD/d_BCD.vhd.    Found 16x7-bit ROM for internal node.    Summary:	inferred   1 ROM(s).Unit <d_bcd> synthesized.Synthesizing Unit <main_bcd>.    Related source file is F:/CPLD_BOARD/d_BCD/main_bcd.vhd.WARNING:Xst:644 - Signal <led2_out<5>> has a multisource.WARNING:Xst:644 - Signal <led2_out<4>> has a multisource.WARNING:Xst:644 - Signal <led2_out<3>> has a multisource.WARNING:Xst:644 - Signal <led2_out<2>> has a multisource.WARNING:Xst:644 - Signal <led2_out<1>> has a multisource.WARNING:Xst:644 - Signal <led2_out<0>> has a multisource.WARNING:Xst:644 - Signal <led2_out<6>> has a multisource.WARNING:Xst:648 -  Output <led3_out<6>> is never used.WARNING:Xst:648 -  Output <led3_out<5>> is never used.WARNING:Xst:648 -  Output <led3_out<4>> is never used.WARNING:Xst:648 -  Output <led3_out<3>> is never used.WARNING:Xst:648 -  Output <led3_out<2>> is never used.WARNING:Xst:648 -  Output <led3_out<1>> is never used.WARNING:Xst:648 -  Output <led3_out<0>> is never used.Unit <main_bcd> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# ROMs                             : 1  16x7-bit ROM                     : 1=========================================================================Starting low level synthesis...Optimizing unit <d_bcd> ...Optimizing unit <main_bcd> ...Merging netlists...=========================================================================Final ResultsOutput File Name                   : main_bcdOutput Format                      : NGCOptimization Criterion             : SpeedTarget Technology                  : 9500xlKeep Hierarchy                     : YESMacro Preserve                     : YESMacro Generation                   : AutoXOR Preserve                       : YESDesign Statistics# Edif Instances                   : 125# I/Os                             : 26=========================================================================CPU : 2.08 / 2.16 s | Elapsed : 2.00 / 2.00 s -->