library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cnt12 is
port(

	clk: in std_logic;
	ena: in std_logic;	
--	set: in std_logic;
--	setdata:in std_logic_vector(3 downto 0);
	co: out std_logic;
	data1,data2: out std_logic_vector(3 downto 0));
end cnt12;

architecture rtl of cnt12 is
    signal tempen:std_logic;
	signal temp1,temp2: std_logic_vector(3 downto 0);

begin
	tempen<=ena;
    process(clk)
    begin
        if clk'event and clk='1' then
           if tempen='1' then
                if temp1="1001" or (temp2="0001" and temp1="0010") then
                   temp1<="0001";
				   if temp2="0001" and temp1="0010" then
					  temp2<="0000";
                   else 
						temp2<=temp2+1;
				   end if ;	
				
                else 
		 			 temp1<=temp1+1;
                end if;
            end if;
        

		end if;
    	
	end process;    
    data1<=temp1;
	data2<=temp2;
 --   tempco<='1' when (temp1="0001" and ena='1') else '0';
	co<='1' when (temp1="0001" and temp2="0010" and ena='1') else '0';
end rtl;