library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity bellcnt10 is
port(
	clk: in std_logic;
	reset,en: in std_logic;	
--	set: in std_logic;
--	setdata:in std_logic_vector(3 downto 0);
	co: out std_logic;
	data1: out std_logic_vector(3 downto 0));
end bellcnt10;

architecture rtl of bellcnt10 is
    signal tempen:std_logic;
	signal temp1: std_logic_vector(3 downto 0);

begin
    process(clk)
    begin
        if clk'event and clk='1' then
		  if reset='1' then
			 temp1<="0000";
           	  elsif en='1' then
                if temp1="1001" then
                   temp1<="0000";
                else 
						temp1<=temp1+1;
				end if ;	
				
           end if;
        end if;
    end process;    
    data1<=temp1;
	 --   tempco<='1' when (temp1="0001" and ena='1') else '0';
	co<='1' when (temp1="1001") else '0';
end rtl;