?? lc2.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lc2 is
port(
en, ien: in std_logic;
oen: out std_logic;
reset: in std_logic
);
end lc2;
architecture rtl of lc2 is
signal temp: std_logic_vector(1 downto 0);
begin
process(ien)
begin
if ien'event and ien='1' then
if reset='1' then
temp<="00";
else
temp<=temp+1;
end if;
end if;
end process;
oen<=temp(0) and en;
end rtl;
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