--
--
------------------------------------------------------------------------------------
-- DESCRIPTION   :  Flip-flop D type
--                  Width: 8
--                  Clock active: high
--                  Synchronous clear active: high
--                  Synchronous set active: high
--                  Clock enable active: high
--                  Load active: high
-- Download from :  http://www.pld.com.cn
------------------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;

entity ffd is
	port (
		CLR : in std_logic;
		SET : in std_logic;
		CE : in std_logic;
		LOAD : in std_logic;
		CLK : in std_logic;
		DATA_IN : in std_logic_vector (7 downto 0);
		DATA_OUT : out std_logic_vector (7 downto 0)
	);
end entity;



architecture ffd_arch of ffd is
signal TEMP_DATA_OUT: std_logic_vector (7 downto 0);
begin

	process (CLK)
	begin

		if rising_edge(CLK) then
			if CE = '1' then
				if CLR = '1' then
					TEMP_DATA_OUT <= (others => '0');
				elsif SET = '1' then
					TEMP_DATA_OUT <= (others => '1');
				elsif LOAD = '1' then
					TEMP_DATA_OUT <= DATA_IN;
				end if;
			end if;
		end if;

	end process;

	DATA_OUT <= TEMP_DATA_OUT;

end architecture;