Release 6.2i - xst G.28Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.95 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.95 s | Elapsed : 0.00 / 1.00 s --> Reading design: top.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis  5) Advanced HDL Synthesis     5.1) HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : top.prjInput Format                       : mixedIgnore Synthesis Constraint File   : NOVerilog Include Directory          : ---- Target ParametersOutput File Name                   : topOutput Format                      : NGCTarget Device                      : xc2v1000-4-fg456---- Source OptionsTop Module Name                    : topAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESMultiplier Style                   : autoAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 500Add Generic Clock Buffer(BUFG)     : 16Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : _Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : top.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESOptimize Instantiated Primitives   : NOtristate2logic                     : No==================================================================================================================================================*                          HDL Compilation                              *=========================================================================WARNING:HDLParsers:3215 - Unit work/TOP is now defined in a different file: was G:/doc/lab6/top.vhd, now is E:/FPGA/Exp6-VGA/top.vhdWARNING:HDLParsers:3215 - Unit work/TOP/BEHAVIORAL is now defined in a different file: was G:/doc/lab6/top.vhd, now is E:/FPGA/Exp6-VGA/top.vhdWARNING:HDLParsers:3215 - Unit work/VGA is now defined in a different file: was G:/doc/lab6/vga.vhd, now is E:/FPGA/Exp6-VGA/vga.vhdWARNING:HDLParsers:3215 - Unit work/VGA/BEHAVIORAL is now defined in a different file: was G:/doc/lab6/vga.vhd, now is E:/FPGA/Exp6-VGA/vga.vhdWARNING:HDLParsers:3215 - Unit work/WRLOGO is now defined in a different file: was G:/doc/lab6/wrlogo.vhd, now is E:/FPGA/Exp6-VGA/wrlogo.vhdWARNING:HDLParsers:3215 - Unit work/WRLOGO/BEHAVIORAL is now defined in a different file: was G:/doc/lab6/wrlogo.vhd, now is E:/FPGA/Exp6-VGA/wrlogo.vhdWARNING:HDLParsers:3481 - No primary, secondary unit in the file E:\FPGA\Exp6-VGA/logo.vhd. Ignore this file from project file top_vhdl.prj.WARNING:HDLParsers:3215 - Unit work/UARTREC is now defined in a different file: was G:/doc/lab6/uartrec.vhd, now is E:/FPGA/Exp6-VGA/uartrec.vhdWARNING:HDLParsers:3215 - Unit work/UARTREC/BEHAVIORAL is now defined in a different file: was G:/doc/lab6/uartrec.vhd, now is E:/FPGA/Exp6-VGA/uartrec.vhdCompiling vhdl file E:/FPGA/Exp6-VGA/uartrec.vhd in Library work.Architecture behavioral of Entity uartrec is up to date.Compiling vhdl file E:/FPGA/Exp6-VGA/wrlogo.vhd in Library work.Architecture behavioral of Entity wrlogo is up to date.Compiling vhdl file E:/FPGA/Exp6-VGA/vga.vhd in Library work.Architecture behavioral of Entity vga is up to date.Compiling vhdl file E:/FPGA/Exp6-VGA/top.vhd in Library work.Architecture behavioral of Entity top is up to date.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <top> (Architecture <behavioral>).INFO:Xst:1739 - HDL ADVISOR - E:/FPGA/Exp6-VGA/top.vhd line 15: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.INFO:Xst:1739 - HDL ADVISOR - E:/FPGA/Exp6-VGA/top.vhd line 16: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.INFO:Xst:1739 - HDL ADVISOR - E:/FPGA/Exp6-VGA/top.vhd line 14: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.INFO:Xst:1739 - HDL ADVISOR - E:/FPGA/Exp6-VGA/top.vhd line 15: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.WARNING:Xst:819 - E:/FPGA/Exp6-VGA/top.vhd line 112: The following signals are missing in the process sensitivity list:   data_sram.WARNING:Xst:819 - E:/FPGA/Exp6-VGA/top.vhd line 121: The following signals are missing in the process sensitivity list:   data_ram, data_srambuf.Entity <top> analyzed. Unit <top> generated.Analyzing Entity <uartrec> (Architecture <behavioral>).WARNING:Xst:766 - E:/FPGA/Exp6-VGA/uartrec.vhd line 39: Generating a Black Box for component <IBUF>.WARNING:Xst:766 - E:/FPGA/Exp6-VGA/uartrec.vhd line 41: Generating a Black Box for component <BUFG>.Entity <uartrec> analyzed. Unit <uartrec> generated.Analyzing Entity <wrlogo> (Architecture <behavioral>).WARNING:Xst:819 - E:/FPGA/Exp6-VGA/wrlogo.vhd line 43: The following signals are missing in the process sensitivity list:   webuf, RxAv, readclk.WARNING:Xst:766 - E:/FPGA/Exp6-VGA/wrlogo.vhd line 107: Generating a Black Box for component <logo>.Entity <wrlogo> analyzed. Unit <wrlogo> generated.Analyzing Entity <vga> (Architecture <behavioral>).WARNING:Xst:819 - E:/FPGA/Exp6-VGA/vga.vhd line 47: The following signals are missing in the process sensitivity list:   hs.Entity <vga> analyzed. Unit <vga> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <vga>.    Related source file is E:/FPGA/Exp6-VGA/vga.vhd.    Found 11-bit comparator greatequal for signal <$n0007> created at line 58.    Found 11-bit comparator less for signal <$n0008> created at line 58.    Found 11-bit comparator greatequal for signal <$n0009> created at line 63.    Found 11-bit comparator less for signal <$n0010> created at line 63.    Found 10-bit up counter for signal <hlocbuf>.    Found 1-bit register for signal <vgaclk>.    Found 10-bit up counter for signal <vlocbuf>.    Summary:	inferred   2 Counter(s).	inferred   1 D-type flip-flop(s).	inferred   4 Comparator(s).Unit <vga> synthesized.Synthesizing Unit <wrlogo>.    Related source file is E:/FPGA/Exp6-VGA/wrlogo.vhd.    Found 8-bit register for signal <dout>.    Found 1-bit register for signal <logo_flag>.    Found 3-bit adder for signal <$n0014> created at line 67.    Found 4-bit adder for signal <$n0015> created at line 67.    Found 10-bit comparator greatequal for signal <$n0019> created at line 99.    Found 10-bit comparator greatequal for signal <$n0020> created at line 67.    Found 10-bit comparator less for signal <$n0021> created at line 67.    Found 10-bit comparator greatequal for signal <$n0022> created at line 67.    Found 10-bit comparator less for signal <$n0023> created at line 67.    Found 13-bit adder for signal <$n0024> created at line 75.    Found 10-bit comparator lessequal for signal <$n0025> created at line 95.    Found 13-bit register for signal <addr>.    Found 10-bit register for signal <inc_x>.    Found 10-bit register for signal <inc_y>.    Found 10-bit up accumulator for signal <mov_x>.    Found 10-bit up accumulator for signal <mov_y>.    Found 1-bit register for signal <readclk>.    Found 1-bit register for signal <webuf>.    Found 1 1-bit 2-to-1 multiplexers.    Summary:	inferred   2 Accumulator(s).	inferred  24 D-type flip-flop(s).	inferred   3 Adder/Subtracter(s).	inferred   6 Comparator(s).	inferred   1 Multiplexer(s).Unit <wrlogo> synthesized.Synthesizing Unit <uartrec>.    Related source file is E:/FPGA/Exp6-VGA/uartrec.vhd.    Found finite state machine <FSM_0> for signal <present_state>.    -----------------------------------------------------------------------    | States             | 3                                              |    | Transitions        | 7                                              |    | Inputs             | 4                                              |    | Outputs            | 3                                              |    | Clock              | recclk (rising_edge)                           |    | Power Up State     | idle                                           |    | Encoding           | automatic                                      |    | Implementation     | LUT                                            |    -----------------------------------------------------------------------    Found 1-bit register for signal <RxAv>.    Found 8-bit register for signal <data>.    Found 3-bit adder for signal <$n0025> created at line 59.    Found 3-bit adder for signal <$n0026> created at line 77.    Found 3-bit register for signal <bitpos>.    Found 3-bit register for signal <cnt>.    Found 8-bit register for signal <data_buf>.    Found 7-bit up counter for signal <divcnt>.    Found 1-bit register for signal <recclk>.    Summary:	inferred   1 Finite State Machine(s).	inferred   1 Counter(s).	inferred  24 D-type flip-flop(s).	inferred   2 Adder/Subtracter(s).Unit <uartrec> synthesized.Synthesizing Unit <top>.    Related source file is E:/FPGA/Exp6-VGA/top.vhd.WARNING:Xst:646 - Signal <weram> is assigned but never used.WARNING:Xst:653 - Signal <data_sram> is used but never assigned. Tied to value 00000000.WARNING:Xst:1780 - Signal <counter> is never used or assigned.WARNING:Xst:1780 - Signal <vgaclk> is never used or assigned.WARNING:Xst:653 - Signal <wesram> is used but never assigned. Tied to value 0.    Found 8 1-bit 2-to-1 multiplexers.    Summary:	inferred   8 Multiplexer(s).Unit <top> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Selecting encoding for FSM_0 ...Optimizing FSM <FSM_0> on signal <present_state> with one-hot encoding.Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# FSMs                             : 1# Adders/Subtractors               : 5 13-bit adder                      : 1 4-bit adder                       : 1 3-bit adder                       : 3# Counters                         : 3 10-bit up counter                 : 2