library verilog;use verilog.vl_types.all;entity clock_alarm_set is    generic(        Time_screen     : integer := 1;        Time_set        : integer := 2;        Date_set        : integer := 4;        Clock_set       : integer := 8;        Sec_clock       : integer := 16;        O_light_set     : integer := 32;        Clock_on        : integer := 4;        Clock_hour      : integer := 2;        Clock_minute    : integer := 1    );    port(        clk_5           : in     vl_logic;        reset           : in     vl_logic;        mode            : in     vl_logic_vector(5 downto 0);        mode_clock      : in     vl_logic_vector(2 downto 0);        set             : in     vl_logic;        keyin           : in     vl_logic;        alm_light_on    : in     vl_logic;        hour_count      : in     vl_logic_vector(7 downto 0);        minute_count    : in     vl_logic_vector(7 downto 0);        clock_h_count   : out    vl_logic_vector(7 downto 0);        clock_m_count   : out    vl_logic_vector(7 downto 0);        alm_light       : out    vl_logic    );end clock_alarm_set;