library verilog;use verilog.vl_types.all;entity second is    generic(        Time_screen     : integer := 1;        Time_set        : integer := 2;        Date_set        : integer := 4;        Clock_set       : integer := 8;        Sec_clock       : integer := 16;        O_light_set     : integer := 32;        Sec_on          : integer := 2;        Sec_stop        : integer := 1;        Sec_reset       : integer := 4    );    port(        clk_100         : in     vl_logic;        reset           : in     vl_logic;        mode            : in     vl_logic_vector(5 downto 0);        mode_sec        : in     vl_logic_vector(2 downto 0);        sec_m_count     : out    vl_logic_vector(7 downto 0);        sec_s_count     : out    vl_logic_vector(7 downto 0);        sec_ms_count    : out    vl_logic_vector(7 downto 0)    );end second;