library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity state is
	port(come:in std_logic;
		re:in std_logic;
		go:out std_logic
		);
end state;

architecture arc_state of state is
signal mode: std_logic;
begin
process(mode)
begin
case mode is
when '0' =>go<='1';
when others =>go<='0';
end case;
end process;

process(re,come)
begin
if re='0' then
mode<='0';
else
if come='1' and come'event then
	mode<=not mode;
end if;
end if;
end process;
end arc_state;