m255cModel Technologydd:\fpga\仿真\dividerEcompact_dividerDP std textio K]Z^fghZ6B=BjnK5NomDT3DP vital2000 vital_primitives P<o@__YgakiANKimF[boN3DP simprim vpackage XeTTF=JmgF?c^E:F;=Azn0DP vital2000 vital_timing S^n>oJ2GS[H5aTKMo9OkE0DP simprim vcomponents ?H8i@hMjl<L:Ddei0QH?M3DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2w1152759292dD:\FPGA\仿真\Divider_定點除法器Fcompact_divider_timesim.vhdl0L22VkLXNUMRV[CDCO0Tk[Omoi3OX;C;5.7g;15o-87 -explicit -O0tExplicit TAstructureDP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1DE simprim x_toc NSEMHf;aClEcCG]830PSf0DE simprim x_roc h7QPjGgL<bNb3[Gli3z;a1DE simprim x_xor2 W;4I9cIPMoTc2;F>8Y@641DE simprim x_one <D0K;n7QZV15LdUciA[nB2DE simprim x_lut4 1PA>fa^ZlY0Bnnoo=6k3l3DE simprim x_mux2 CMcL@9I:aEF[ao=Z>QdC]3DE simprim x_zero N^U=T=[a8c=0?VcPXJKkl3DE simprim x_buf g>zldXRLeD9S;Mi<MUBN:1DE simprim x_inv k]WfT4nk10LehOI:JGmHH0DE simprim x_tri b^9c9K]XkdcB9^?Xmgnjd2DP std textio K]Z^fghZ6B=BjnK5NomDT3DP vital2000 vital_primitives P<o@__YgakiANKimF[boN3DP simprim vpackage XeTTF=JmgF?c^E:F;=Azn0DP vital2000 vital_timing S^n>oJ2GS[H5aTKMo9OkE0DP simprim vcomponents ?H8i@hMjl<L:Ddei0QH?M3DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work compact_divider kLXNUMRV[CDCO0Tk[Omoi3l228L32VFdgk2H@fjV6KANQfzeECF3OX;C;5.7g;15M7 ieee std_logic_1164M6 simprim vcomponentsM5 vital2000 vital_timingM4 simprim vpackageM3 vital2000 vital_primitivesM2 std textioM1 ieee vital_timingo-87 -explicit -O0tExplicit TAbehavioralDP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work compact_divider :JhJo`4oz14`lFgTgR^me1l24L22VmR5V9kn@]zY;@DkP64jh@2OX;C;5.7g;1531M3 ieee std_logic_1164M2 ieee std_logic_arithM1 ieee std_logic_unsignedo-93 -explicit -O0tExplicit Tdd:\fpga\仿真\dividerFcompact_divider.vhdlw1148873959Ccompact_divider_cfgDA work t_compact testbench_arch 9k7mEeRU_XM?=iN3YlTGL0DP std textio K]Z^fghZ6B=BjnK5NomDT3DP ieee std_logic_textio 8YS?iX`WD1REQG`ZRYQGB2DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work t_compact _8<DC9oda>mj^30KIgfc:0w1152759293dD:\FPGA\仿真\Divider_定點除法器Ft_compact.timesim_vhwl0L0V3JK_mk1NkJ2gCG9M<:A1m1OX;C;5.7g;1531M5 ieee std_logic_1164M4 ieee std_logic_arithM3 ieee std_logic_unsignedM2 ieee std_logic_textioM1 std textioatestbench_archet_compacto-93 -explicit -O0tExplicit TEdeviderDP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2w1148873631dD:\FPGA\仿真\Divider_定點除法器Fdevider.vhdll0L11Vn63=@:f0DP:O_i8N<G[<H0OX;C;5.7g;1531o-93 -explicit -O0tExplicit TAbehavioralDP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work devider n63=@:f0DP:O_i8N<G[<H0l22L20V3e4JL;e_lb?co7aGUDmm22OX;C;5.7g;1531M3 ieee std_logic_1164M2 ieee std_logic_arithM1 ieee std_logic_unsignedo-93 -explicit -O0tExplicit TAstructureDP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1DE simprim x_toc NSEMHf;aClEcCG]830PSf0DE simprim x_roc h7QPjGgL<bNb3[Gli3z;a1DE simprim x_xor2 W;4I9cIPMoTc2;F>8Y@641DE simprim x_one <D0K;n7QZV15LdUciA[nB2DE simprim x_lut4 1PA>fa^ZlY0Bnnoo=6k3l3DE simprim x_mux2 CMcL@9I:aEF[ao=Z>QdC]3DE simprim x_zero N^U=T=[a8c=0?VcPXJKkl3DE simprim x_buf g>zldXRLeD9S;Mi<MUBN:1DE simprim x_inv k]WfT4nk10LehOI:JGmHH0DE simprim x_tri b^9c9K]XkdcB9^?Xmgnjd2DP std textio K]Z^fghZ6B=BjnK5NomDT3DP vital2000 vital_primitives P<o@__YgakiANKimF[boN3DP simprim vpackage XeTTF=JmgF?c^E:F;=Azn0DP vital2000 vital_timing S^n>oJ2GS[H5aTKMo9OkE0DP simprim vcomponents ?H8i@hMjl<L:Ddei0QH?M3DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work devider R=X16UmXDzIz8e@3H9zzk1l228L32V8CznUZBh<zFhn7M3<963H0OX;C;5.7g;15M7 ieee std_logic_1164M6 simprim vcomponentsM5 vital2000 vital_timingM4 simprim vpackageM3 vital2000 vital_primitivesM2 std textioM1 ieee vital_timingo-87 -explicit -O0tExplicit TFdevider_timesim.vhdw1152759483Cdevider_cfgDE work devider n63=@:f0DP:O_i8N<G[<H0DA work t_divider testbench_arch M@^ZfO144h1]S27:44U[U3DP std textio K]Z^fghZ6B=BjnK5NomDT3DP ieee std_logic_textio 8YS?iX`WD1REQG`ZRYQGB2DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work t_divider @XH==BeFTd`jGS@mKmmR;0w1152759597dD:\FPGA\仿真\Divider_定點除法器Ft_divider.vhwl0L0VB2O=o^8b8K]oQ@Oh^I3EB1OX;C;5.7g;1531M5 ieee std_logic_1164M4 ieee std_logic_arithM3 ieee std_logic_unsignedM2 ieee std_logic_textioM1 std textioatestbench_archet_dividero-93 -explicit -O0tExplicit TEt_compactDP std textio K]Z^fghZ6B=BjnK5NomDT3DP ieee std_logic_textio 8YS?iX`WD1REQG`ZRYQGB2DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2w1152759293dD:\FPGA\仿真\Divider_定點除法器Ft_compact.timesim_vhwl0L21V_8<DC9oda>mj^30KIgfc:0OX;C;5.7g;1531o-93 -explicit -O0tExplicit TAtestbench_archDP std textio K]Z^fghZ6B=BjnK5NomDT3DP ieee std_logic_textio 8YS?iX`WD1REQG`ZRYQGB2DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work t_compact _8<DC9oda>mj^30KIgfc:0l47L24V9k7mEeRU_XM?=iN3YlTGL0OX;C;5.7g;1531M5 ieee std_logic_1164M4 ieee std_logic_arithM3 ieee std_logic_unsignedM2 ieee std_logic_textioM1 std textioo-93 -explicit -O0tExplicit TEt_dividerDP std textio K]Z^fghZ6B=BjnK5NomDT3DP ieee std_logic_textio 8YS?iX`WD1REQG`ZRYQGB2DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2w1152759597dD:\FPGA\仿真\Divider_定點除法器Ft_divider.vhwl0L21V@XH==BeFTd`jGS@mKmmR;0OX;C;5.7g;1531o-93 -explicit -O0tExplicit TAtestbench_archDE work devider n63=@:f0DP:O_i8N<G[<H0DP std textio K]Z^fghZ6B=BjnK5NomDT3DP ieee std_logic_textio 8YS?iX`WD1REQG`ZRYQGB2DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work t_divider @XH==BeFTd`jGS@mKmmR;0l44L24VM@^ZfO144h1]S27:44U[U3OX;C;5.7g;1531M5 ieee std_logic_1164M4 ieee std_logic_arithM3 ieee std_logic_unsignedM2 ieee std_logic_textioM1 std textioo-93 -explicit -O0tExplicit T