-- D:\FPGA\仿真\DIVIDER_定點除法器
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Jul 13 10:54:53 2006
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY t_compact IS
END t_compact;

ARCHITECTURE testbench_arch OF t_compact IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT compact_divider
		GENERIC (
			n : INTEGER
		);
		PORT (
			a : In  INTEGER RANGE 0 TO 15;
			b : In  INTEGER RANGE 0 TO 15;
			y : Out  std_logic_vector (3 DOWNTO 0);
			rest : Out  INTEGER RANGE 0 TO 15;
			err : Out  std_logic
		);
	END COMPONENT;

	SIGNAL a : INTEGER RANGE 0 TO 15;
	SIGNAL b : INTEGER RANGE 0 TO 15;
	SIGNAL y : std_logic_vector (3 DOWNTO 0);
	SIGNAL rest : INTEGER RANGE 0 TO 15;
	SIGNAL err : std_logic;

BEGIN
	UUT : compact_divider
	GENERIC MAP (
		n => 3
	)
	PORT MAP (
		a => a,
		b => b,
		y => y,
		rest => rest,
		err => err
	);

	PROCESS
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_y(
			next_y : std_logic_vector (3 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (y /= next_y) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("us y="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, y);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_y);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_rest(
			next_rest : INTEGER;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (rest /= next_rest) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("us rest="));
				STD.TEXTIO.write(TX_LOC, rest);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				STD.TEXTIO.write(TX_LOC, next_rest);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_err(
			next_err : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (err /= next_err) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("us err="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, err);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_err);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		a <= transport 0; -- 0
		b <= transport 0; -- 0
		-- --------------------
		WAIT FOR 100 us; -- Time=100 us
		a <= transport 1; -- 1
		b <= transport 0; -- 0
		-- --------------------
		WAIT FOR 100 us; -- Time=200 us
		a <= transport 2; -- 2
		b <= transport 1; -- 1
		-- --------------------
		WAIT FOR 100 us; -- Time=300 us
		a <= transport 3; -- 3
		b <= transport 2; -- 2
		-- --------------------
		WAIT FOR 100 us; -- Time=400 us
		a <= transport 4; -- 4
		b <= transport 0; -- 0
		-- --------------------
		WAIT FOR 100 us; -- Time=500 us
		a <= transport 5; -- 5
		b <= transport 1; -- 1
		-- --------------------
		WAIT FOR 100 us; -- Time=600 us
		a <= transport 6; -- 6
		b <= transport 2; -- 2
		-- --------------------
		WAIT FOR 100 us; -- Time=700 us
		a <= transport 7; -- 7
		b <= transport 0; -- 0
		-- --------------------
		WAIT FOR 100 us; -- Time=800 us
		b <= transport 1; -- 1
		-- --------------------
		WAIT FOR 500 us; -- Time=1300 us
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION compact_divider_cfg OF t_compact IS
	FOR testbench_arch
	END FOR;
END compact_divider_cfg;