?? urat.rpt
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Project Information d:\maxplus2\file\uart\urat.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 04/30/2004 11:38:35
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
urat EPF10K10LC84-4 12 26 0 0 0 % 75 13 %
User Pins: 12 26 0
Project Information d:\maxplus2\file\uart\urat.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Ignored logic function symbol "m16" (ID :25) -- it has no output
Project Information d:\maxplus2\file\uart\urat.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
urat@42 Fs_load
urat@53 Fs_pi0
urat@52 Fs_pi1
urat@51 Fs_pi2
urat@50 Fs_pi3
urat@49 Fs_pi4
urat@48 Fs_pi5
urat@47 Fs_pi6
urat@44 Fs_pi7
urat@37 Fs_Txd
urat@24 js_po0
urat@23 js_po1
urat@22 js_po2
urat@21 js_po3
urat@19 js_po4
urat@18 js_po5
urat@17 js_po6
urat@16 js_po7
urat@30 Js_Rxd
urat@35 20Mhz
Project Information d:\maxplus2\file\uart\urat.rpt
** FILE HIERARCHY **
|m16:25|
|s_clk:40|
|g1p:77|
|g1p:116|
|js_tb:93|
|js_sft:95|
|fs_cnt:113|
|fs_sft:115|
Device-Specific Information: d:\maxplus2\file\uart\urat.rpt
urat
***** Logic for device 'urat' compiled without errors.
Device: EPF10K10LC84-4
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
^
C
R R R R R R f R R R R O
E E E E E E s E E E E N
S S S S j J S V S G _ G S G F S S S F
E E E E s s E C E N c N E N s E E E _ ^
R R R R _ _ R C R D l D R D _ R R R # D n
V V V V c d V I V I o I V I p V V V T O C
E E E E l a E N E N c N E N o E E E C N E
D D D D k o D T D T k T D T 8 D D D K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | RESERVED
^nCE | 14 72 | RESERVED
#TDI | 15 71 | RESERVED
js_po7 | 16 70 | 1p
js_po6 | 17 69 | RESERVED
js_po5 | 18 68 | GNDINT
js_po4 | 19 67 | RESERVED
VCCINT | 20 66 | fs_ld
js_po3 | 21 65 | fs_1p
js_po2 | 22 EPF10K10LC84-4 64 | RESERVED
js_po1 | 23 63 | VCCINT
js_po0 | 24 62 | fs_dao
Fs_po0 | 25 61 | Fs_po4
GNDINT | 26 60 | Fs_po6
Fs_po5 | 27 59 | fs_clk
Fs_po7 | 28 58 | Fs_po1
Fs_po3 | 29 57 | #TMS
Js_Rxd | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | Fs_po9
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ 2 R F F R V G F G F V G F F F F F F F
C n 0 E s s E C N s N s C N s s s s s s s
C C M S _ _ S C D _ D _ C D _ _ _ _ _ _ _
I O h E T p E I I l I p I I p p p p p p p
N N z R x o R N N o N i N N i i i i i i i
T F V d 2 V T T a T 7 T T 6 5 4 3 2 1 0
I E E d
G D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\maxplus2\file\uart\urat.rpt
urat
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
A3 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 3/22( 13%)
A8 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 2/2 4/22( 18%)
A11 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 0/2 3/22( 13%)
B7 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 0/2 3/22( 13%)
C4 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
C7 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
C9 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 1/2 1/2 7/22( 31%)
C16 7/ 8( 87%) 2/ 8( 25%) 4/ 8( 50%) 2/2 1/2 5/22( 22%)
C17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
C18 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 2/22( 9%)
C22 3/ 8( 37%) 2/ 8( 25%) 1/ 8( 12%) 1/2 1/2 4/22( 18%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 3/6 ( 50%)
Total I/O pins used: 35/53 ( 66%)
Total logic cells used: 75/576 ( 13%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 2.21/4 ( 55%)
Total fan-in: 166/2304 ( 7%)
Total input pins required: 12
Total input I/O cell registers required: 0
Total output pins required: 26
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 75
Total flipflops required: 53
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 5/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 1 8 0 0 0 0 8 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25/0
B: 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8/0
C: 0 0 0 8 0 0 8 0 8 0 0 0 0 0 0 0 7 1 7 0 0 0 3 0 0 42/0
Total: 0 1 8 8 0 0 16 8 8 0 8 0 0 0 0 0 7 1 7 0 0 0 3 0 0 75/0
Device-Specific Information: d:\maxplus2\file\uart\urat.rpt
urat
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
1 - - - -- INPUT G 0 0 0 2 fs_clock
42 - - - -- INPUT G 0 0 0 0 Fs_load
53 - - - 20 INPUT 0 0 0 1 Fs_pi0
52 - - - 19 INPUT 0 0 0 1 Fs_pi1
51 - - - 18 INPUT 0 0 0 1 Fs_pi2
50 - - - 17 INPUT 0 0 0 1 Fs_pi3
49 - - - 16 INPUT 0 0 0 1 Fs_pi4
48 - - - 15 INPUT 0 0 0 1 Fs_pi5
47 - - - 14 INPUT 0 0 0 1 Fs_pi6
44 - - - -- INPUT 0 0 0 1 Fs_pi7
30 - - C -- INPUT 0 0 0 2 Js_Rxd
35 - - - 06 INPUT 0 0 0 8 20Mhz
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
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