?? urat.rpt
字號:
_LC3_A8 = DFFE( _EQ012, !_LC1_C4, !_LC8_A8, VCC, VCC);
_EQ012 = _LC2_A3 & !_LC3_A8
# !_LC2_A3 & _LC3_A8;
-- Node name is '|js_tb:93|jsck1' from file "js_tb.tdf" line 8, column 6
-- Equation name is '_LC2_A8', type is buried
_LC2_A8 = DFFE( _EQ013, !_LC1_C4, !_LC8_A8, VCC, VCC);
_EQ013 = _LC2_A3 & !_LC2_A8 & _LC3_A8
# _LC2_A8 & !_LC3_A8
# !_LC2_A3 & _LC2_A8;
-- Node name is '|js_tb:93|jsck2' from file "js_tb.tdf" line 8, column 6
-- Equation name is '_LC4_A8', type is buried
_LC4_A8 = DFFE( _EQ014, !_LC1_C4, !_LC8_A8, VCC, VCC);
_EQ014 = !_LC3_A8 & _LC4_A8
# !_LC2_A8 & _LC4_A8
# _LC2_A3 & _LC2_A8 & _LC3_A8 & !_LC4_A8
# !_LC2_A3 & _LC4_A8;
-- Node name is '|js_tb:93|jsck3' from file "js_tb.tdf" line 8, column 6
-- Equation name is '_LC8_A3', type is buried
_LC8_A3 = DFFE( _EQ015, !_LC1_C4, !_LC8_A8, VCC, VCC);
_EQ015 = !_LC1_A8 & _LC8_A3
# _LC1_A8 & _LC2_A3 & !_LC8_A3
# !_LC2_A3 & _LC8_A3;
-- Node name is '|js_tb:93|jsck4' from file "js_tb.tdf" line 8, column 6
-- Equation name is '_LC6_A3', type is buried
_LC6_A3 = DFFE( _EQ016, !_LC1_C4, !_LC8_A8, VCC, VCC);
_EQ016 = _LC6_A3 & !_LC8_A3
# !_LC1_A8 & _LC6_A3
# _LC1_A8 & _LC2_A3 & !_LC6_A3 & _LC8_A3
# !_LC2_A3 & _LC6_A3;
-- Node name is '|js_tb:93|jsck5' from file "js_tb.tdf" line 8, column 6
-- Equation name is '_LC5_A3', type is buried
_LC5_A3 = DFFE( _EQ017, !_LC1_C4, !_LC8_A8, VCC, VCC);
_EQ017 = _LC2_A3 & !_LC3_A3 & _LC5_A3
# _LC2_A3 & _LC3_A3 & !_LC5_A3
# _LC4_A3 & _LC5_A3;
-- Node name is '|js_tb:93|jsck6' from file "js_tb.tdf" line 8, column 6
-- Equation name is '_LC7_A3', type is buried
_LC7_A3 = DFFE( _EQ018, !_LC1_C4, !_LC8_A8, VCC, VCC);
_EQ018 = !_LC5_A3 & _LC7_A3
# !_LC3_A3 & _LC7_A3
# _LC3_A3 & !_LC4_A3 & _LC5_A3 & !_LC7_A3
# _LC4_A3 & _LC7_A3;
-- Node name is '|js_tb:93|jsck7' from file "js_tb.tdf" line 8, column 6
-- Equation name is '_LC4_A3', type is buried
_LC4_A3 = DFFE( _EQ019, !_LC1_C4, !_LC8_A8, VCC, VCC);
_EQ019 = _LC4_A3
# _LC3_A3 & _LC5_A3 & _LC7_A3;
-- Node name is '|js_tb:93|:54' from file "js_tb.tdf" line 14, column 16
-- Equation name is '_LC2_A3', type is buried
!_LC2_A3 = _LC2_A3~NOT;
_LC2_A3~NOT = LCELL( _EQ020);
_EQ020 = _LC4_A3 & _LC7_A3
# _LC4_A3 & _LC5_A3;
-- Node name is '|js_tb:93|:65' from file "js_tb.tdf" line 15, column 21
-- Equation name is '_LC1_A8', type is buried
_LC1_A8 = LCELL( _EQ021);
_EQ021 = _LC2_A8 & _LC3_A8 & _LC4_A8;
-- Node name is '|js_tb:93|:73' from file "js_tb.tdf" line 15, column 21
-- Equation name is '_LC3_A3', type is buried
_LC3_A3 = LCELL( _EQ022);
_EQ022 = _LC1_A8 & _LC6_A3 & _LC8_A3;
-- Node name is '|js_tb:93|:122' from file "js_tb.tdf" line 20, column 20
-- Equation name is '_LC1_A3', type is buried
!_LC1_A3 = _LC1_A3~NOT;
_LC1_A3~NOT = LCELL( _EQ023);
_EQ023 = _LC4_A3 & _LC5_A3 & !_LC6_A3 & !_LC7_A3;
-- Node name is '|s_clk:40|fp0' from file "s_clk.tdf" line 8, column 4
-- Equation name is '_LC8_C4', type is buried
_LC8_C4 = DFFE( _EQ024, 20Mhz, VCC, VCC, VCC);
_EQ024 = _LC1_C7 & !_LC5_C4 & !_LC8_C4
# !_LC7_C4 & !_LC8_C4;
-- Node name is '|s_clk:40|fp1' from file "s_clk.tdf" line 8, column 4
-- Equation name is '_LC6_C4', type is buried
_LC6_C4 = DFFE( _EQ025, 20Mhz, VCC, VCC, VCC);
_EQ025 = !_LC2_C4 & !_LC6_C4 & _LC8_C4
# !_LC2_C4 & _LC6_C4 & !_LC8_C4;
-- Node name is '|s_clk:40|fp2' from file "s_clk.tdf" line 8, column 4
-- Equation name is '_LC4_C4', type is buried
_LC4_C4 = DFFE( _EQ026, 20Mhz, VCC, VCC, VCC);
_EQ026 = !_LC2_C4 & _LC4_C4 & !_LC5_C4
# !_LC2_C4 & !_LC4_C4 & _LC5_C4;
-- Node name is '|s_clk:40|fp3' from file "s_clk.tdf" line 8, column 4
-- Equation name is '_LC4_C7', type is buried
_LC4_C7 = DFFE( _EQ027, 20Mhz, VCC, VCC, VCC);
_EQ027 = !_LC2_C4 & !_LC3_C4 & _LC4_C7
# !_LC2_C4 & _LC3_C4 & !_LC4_C7;
-- Node name is '|s_clk:40|fp4' from file "s_clk.tdf" line 8, column 4
-- Equation name is '_LC5_C7', type is buried
_LC5_C7 = DFFE( _EQ028, 20Mhz, VCC, VCC, VCC);
_EQ028 = !_LC2_C4 & !_LC4_C7 & _LC5_C7
# !_LC2_C4 & !_LC3_C4 & _LC5_C7
# !_LC2_C4 & _LC3_C4 & _LC4_C7 & !_LC5_C7;
-- Node name is '|s_clk:40|fp5' from file "s_clk.tdf" line 8, column 4
-- Equation name is '_LC7_C7', type is buried
_LC7_C7 = DFFE( _EQ029, 20Mhz, VCC, VCC, VCC);
_EQ029 = !_LC2_C4 & !_LC6_C7 & _LC7_C7
# !_LC2_C4 & !_LC5_C7 & _LC7_C7
# !_LC2_C4 & _LC5_C7 & _LC6_C7 & !_LC7_C7;
-- Node name is '|s_clk:40|fp6' from file "s_clk.tdf" line 8, column 4
-- Equation name is '_LC2_C7', type is buried
_LC2_C7 = DFFE( _EQ030, 20Mhz, VCC, VCC, VCC);
_EQ030 = !_LC2_C4 & _LC2_C7 & !_LC8_C7
# !_LC2_C4 & !_LC2_C7 & _LC8_C7;
-- Node name is '|s_clk:40|fp7' from file "s_clk.tdf" line 8, column 4
-- Equation name is '_LC7_C4', type is buried
_LC7_C4 = DFFE( _EQ031, 20Mhz, VCC, VCC, VCC);
_EQ031 = !_LC2_C4 & !_LC2_C7 & _LC7_C4
# !_LC2_C4 & _LC7_C4 & !_LC8_C7
# !_LC2_C4 & _LC2_C7 & !_LC7_C4 & _LC8_C7;
-- Node name is '|s_clk:40|:44' from file "s_clk.tdf" line 11, column 13
-- Equation name is '_LC1_C4', type is buried
!_LC1_C4 = _LC1_C4~NOT;
_LC1_C4~NOT = LCELL( _EQ032);
_EQ032 = _LC1_C7 & !_LC6_C4 & !_LC7_C4 & _LC8_C4;
-- Node name is '|s_clk:40|:47' from file "s_clk.tdf" line 13, column 10
-- Equation name is '_LC5_C4', type is buried
_LC5_C4 = LCELL( _EQ033);
_EQ033 = _LC6_C4 & _LC8_C4;
-- Node name is '|s_clk:40|~53~1' from file "s_clk.tdf" line 13, column 10
-- Equation name is '_LC3_C7', type is buried
-- synthesized logic cell
_LC3_C7 = LCELL( _EQ034);
_EQ034 = !_LC4_C4 & !_LC4_C7 & !_LC5_C7;
-- Node name is '|s_clk:40|~53~2' from file "s_clk.tdf" line 13, column 10
-- Equation name is '_LC1_C7', type is buried
-- synthesized logic cell
_LC1_C7 = LCELL( _EQ035);
_EQ035 = !_LC2_C7 & _LC3_C7 & !_LC7_C7;
-- Node name is '|s_clk:40|:55' from file "s_clk.tdf" line 13, column 10
-- Equation name is '_LC2_C4', type is buried
!_LC2_C4 = _LC2_C4~NOT;
_LC2_C4~NOT = LCELL( _EQ036);
_EQ036 = !_LC7_C4
# _LC1_C7 & !_LC5_C4;
-- Node name is '|s_clk:40|:66' from file "s_clk.tdf" line 16, column 14
-- Equation name is '_LC3_C4', type is buried
_LC3_C4 = LCELL( _EQ037);
_EQ037 = _LC4_C4 & _LC5_C4;
-- Node name is '|s_clk:40|:70' from file "s_clk.tdf" line 16, column 14
-- Equation name is '_LC6_C7', type is buried
_LC6_C7 = LCELL( _EQ038);
_EQ038 = _LC3_C4 & _LC4_C7;
-- Node name is '|s_clk:40|:78' from file "s_clk.tdf" line 16, column 14
-- Equation name is '_LC8_C7', type is buried
_LC8_C7 = LCELL( _EQ039);
_EQ039 = _LC3_C4 & _LC4_C7 & _LC5_C7 & _LC7_C7;
-- Node name is ':29'
-- Equation name is '_LC5_A8', type is buried
_LC5_A8 = LCELL( _EQ040);
_EQ040 = !Js_Rxd & !_LC1_A3;
-- Node name is ':117'
-- Equation name is '_LC2_C16', type is buried
!_LC2_C16 = _LC2_C16~NOT;
_LC2_C16~NOT = LCELL( _EQ041);
_EQ041 = _LC1_C16
# !_LC8_C16;
Project Information d:\maxplus2\file\uart\urat.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,497K
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