-- Vhdl instantiation template created from schematic top.sch - Thu Apr 06 09:31:43 2006
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module.
-- 2) To use this template to instantiate this component, cut-and-paste and then edit.
--

   COMPONENT top
   PORT( CS1	:	OUT	STD_LOGIC; 
          A0	:	IN	STD_LOGIC; 
          A1	:	IN	STD_LOGIC; 
          A2	:	IN	STD_LOGIC; 
          CS	:	IN	STD_LOGIC; 
          SEN0	:	OUT	STD_LOGIC; 
          REL0	:	OUT	STD_LOGIC; 
          M1PS	:	OUT	STD_LOGIC; 
          M1CLR	:	OUT	STD_LOGIC; 
          SEN1	:	OUT	STD_LOGIC; 
          PC1ON	:	OUT	STD_LOGIC; 
          SPDA1	:	OUT	STD_LOGIC; 
          SPDB1	:	OUT	STD_LOGIC; 
          M2PS	:	OUT	STD_LOGIC; 
          M2SG	:	OUT	STD_LOGIC; 
          M2CLR	:	OUT	STD_LOGIC; 
          SEN2	:	OUT	STD_LOGIC; 
          SPDB2	:	OUT	STD_LOGIC; 
          PC2ON	:	OUT	STD_LOGIC; 
          WR	:	IN	STD_LOGIC; 
          RESET	:	IN	STD_LOGIC; 
          SPD2A	:	OUT	STD_LOGIC; 
          M1SG	:	OUT	STD_LOGIC; 
          D	:	INOUT	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          MR_0	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          MR_1	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          MR_2	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          MPOS0	:	OUT	STD_LOGIC; 
          MNEG0	:	OUT	STD_LOGIC; 
          UART0	:	OUT	STD_LOGIC; 
          INT_L0	:	IN	STD_LOGIC; 
          CLK8	:	IN	STD_LOGIC; 
          ALMR	:	OUT	STD_LOGIC; 
          INT0	:	OUT	STD_LOGIC; 
          CLK	:	OUT	STD_LOGIC; 
          MC0	:	IN	STD_LOGIC; 
          MB0	:	IN	STD_LOGIC; 
          MA0	:	IN	STD_LOGIC);
   END COMPONENT;

   UUT: top PORT MAP(
		CS1 => , 
		A0 => , 
		A1 => , 
		A2 => , 
		CS => , 
		SEN0 => , 
		REL0 => , 
		M1PS => , 
		M1CLR => , 
		SEN1 => , 
		PC1ON => , 
		SPDA1 => , 
		SPDB1 => , 
		M2PS => , 
		M2SG => , 
		M2CLR => , 
		SEN2 => , 
		SPDB2 => , 
		PC2ON => , 
		WR => , 
		RESET => , 
		SPD2A => , 
		M1SG => , 
		D => , 
		MR_0 => , 
		MR_1 => , 
		MR_2 => , 
		MPOS0 => , 
		MNEG0 => , 
		UART0 => , 
		INT_L0 => , 
		CLK8 => , 
		ALMR => , 
		INT0 => , 
		CLK => , 
		MC0 => , 
		MB0 => , 
		MA0 => 
   );