?? testwave.vhw
字號:
-- D:\FPGA\TEST\XC_9572
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Apr 06 17:11:47 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
-- - Save it as a file with a .vhd extension (i.e. File->Save As...)
-- - Add it to your project as a testbench source (i.e. Project->Add Source...)
--
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.NUMERIC_STD.ALL;USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY testwave IS
END testwave;
ARCHITECTURE testbench_arch OF testwave IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
COMPONENT top
PORT (
A0 : In std_logic;
A1 : In std_logic;
A2 : In std_logic;
CLK8 : In std_logic;
CS : In std_logic;
INT_L0 : In std_logic;
MA0 : In std_logic;
MA1 : In std_logic;
MB0 : In std_logic;
MB1 : In std_logic;
MC0 : In std_logic;
MC1 : In std_logic;
MR_0 : In std_logic_vector (7 DOWNTO 0);
MR_1 : In std_logic_vector (7 DOWNTO 0);
MR_2 : In std_logic_vector (7 DOWNTO 0);
RD : In std_logic;
RESET : In std_logic;
WR : In std_logic;
ALMR : Out std_logic;
CLK : Out std_logic;
CS1 : Out std_logic;
INT0 : Out std_logic;
M1CLR : Out std_logic;
M1PS : Out std_logic;
M1SG : Out std_logic;
M2CLR : Out std_logic;
M2PS : Out std_logic;
M2SG : Out std_logic;
PC1ON : Out std_logic;
PC2ON : Out std_logic;
REL0 : Out std_logic;
SEN0 : Out std_logic;
SEN1 : Out std_logic;
SEN2 : Out std_logic;
SPDA1 : Out std_logic;
SPDB1 : Out std_logic;
SPDB2 : Out std_logic;
SPD2A : Out std_logic;
UART0 : Out std_logic;
D : InOut std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
SIGNAL A0 : std_logic;
SIGNAL A1 : std_logic;
SIGNAL A2 : std_logic;
SIGNAL CLK8 : std_logic;
SIGNAL CS : std_logic;
SIGNAL INT_L0 : std_logic;
SIGNAL MA0 : std_logic;
SIGNAL MA1 : std_logic;
SIGNAL MB0 : std_logic;
SIGNAL MB1 : std_logic;
SIGNAL MC0 : std_logic;
SIGNAL MC1 : std_logic;
SIGNAL MR_0 : std_logic_vector (7 DOWNTO 0);
SIGNAL MR_1 : std_logic_vector (7 DOWNTO 0);
SIGNAL MR_2 : std_logic_vector (7 DOWNTO 0);
SIGNAL RD : std_logic;
SIGNAL RESET : std_logic;
SIGNAL WR : std_logic;
SIGNAL ALMR : std_logic;
SIGNAL CLK : std_logic;
SIGNAL CS1 : std_logic;
SIGNAL INT0 : std_logic;
SIGNAL M1CLR : std_logic;
SIGNAL M1PS : std_logic;
SIGNAL M1SG : std_logic;
SIGNAL M2CLR : std_logic;
SIGNAL M2PS : std_logic;
SIGNAL M2SG : std_logic;
SIGNAL PC1ON : std_logic;
SIGNAL PC2ON : std_logic;
SIGNAL REL0 : std_logic;
SIGNAL SEN0 : std_logic;
SIGNAL SEN1 : std_logic;
SIGNAL SEN2 : std_logic;
SIGNAL SPDA1 : std_logic;
SIGNAL SPDB1 : std_logic;
SIGNAL SPDB2 : std_logic;
SIGNAL SPD2A : std_logic;
SIGNAL UART0 : std_logic;
SIGNAL D : std_logic_vector (7 DOWNTO 0);
BEGIN
UUT : top
PORT MAP (
A0 => A0,
A1 => A1,
A2 => A2,
CLK8 => CLK8,
CS => CS,
INT_L0 => INT_L0,
MA0 => MA0,
MA1 => MA1,
MB0 => MB0,
MB1 => MB1,
MC0 => MC0,
MC1 => MC1,
MR_0 => MR_0,
MR_1 => MR_1,
MR_2 => MR_2,
RD => RD,
RESET => RESET,
WR => WR,
ALMR => ALMR,
CLK => CLK,
CS1 => CS1,
INT0 => INT0,
M1CLR => M1CLR,
M1PS => M1PS,
M1SG => M1SG,
M2CLR => M2CLR,
M2PS => M2PS,
M2SG => M2SG,
PC1ON => PC1ON,
PC2ON => PC2ON,
REL0 => REL0,
SEN0 => SEN0,
SEN1 => SEN1,
SEN2 => SEN2,
SPDA1 => SPDA1,
SPDB1 => SPDB1,
SPDB2 => SPDB2,
SPD2A => SPD2A,
UART0 => UART0,
D => D
);
PROCESS -- clock process for CLK8,
BEGIN
CLOCK_LOOP : LOOP
CLK8 <= transport '0';
WAIT FOR 10 ns;
CLK8 <= transport '1';
WAIT FOR 10 ns;
WAIT FOR 40 ns;
CLK8 <= transport '0';
WAIT FOR 40 ns;
END LOOP CLOCK_LOOP;
END PROCESS;
PROCESS -- Process for CLK8
VARIABLE TX_OUT : LINE;
VARIABLE TX_ERROR : INTEGER := 0;
PROCEDURE CHECK_ALMR(
next_ALMR : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (ALMR /= next_ALMR) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns ALMR="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, ALMR);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_ALMR);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_CLK(
next_CLK : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (CLK /= next_CLK) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns CLK="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, CLK);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_CLK);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_CS1(
next_CS1 : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (CS1 /= next_CS1) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns CS1="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, CS1);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_CS1);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_INT0(
next_INT0 : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (INT0 /= next_INT0) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns INT0="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, INT0);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_INT0);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_M1CLR(
next_M1CLR : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (M1CLR /= next_M1CLR) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns M1CLR="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, M1CLR);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_M1CLR);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_M1PS(
next_M1PS : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (M1PS /= next_M1PS) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns M1PS="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, M1PS);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_M1PS);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_M1SG(
next_M1SG : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (M1SG /= next_M1SG) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns M1SG="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, M1SG);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_M1SG);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_M2CLR(
next_M2CLR : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (M2CLR /= next_M2CLR) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns M2CLR="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, M2CLR);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_M2CLR);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_M2PS(
next_M2PS : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (M2PS /= next_M2PS) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns M2PS="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, M2PS);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_M2PS);
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