-- D:\FPGA\XC_9572
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Tue Apr 25 14:49:45 2006
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY countt1 IS
END countt1;

ARCHITECTURE testbench_arch OF countt1 IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT count4
		PORT (
			CE : In  std_logic;
			CLR : In  std_logic;
			UP : In  std_logic_vector (1 DOWNTO 0);
			CCLK : In  std_logic;
			Qout : Out  std_logic_vector (3 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL CE : std_logic;
	SIGNAL CLR : std_logic;
	SIGNAL UP : std_logic_vector (1 DOWNTO 0);
	SIGNAL CCLK : std_logic;
	SIGNAL Qout : std_logic_vector (3 DOWNTO 0);

BEGIN
	UUT : count4
	PORT MAP (
		CE => CE,
		CLR => CLR,
		UP => UP,
		CCLK => CCLK,
		Qout => Qout
	);

	PROCESS
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_Qout(
			next_Qout : std_logic_vector (3 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (Qout /= next_Qout) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns Qout="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Qout);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_Qout);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		CE <= transport '0';
		CLR <= transport '1';
		UP <= transport std_logic_vector'("00"); --0
		CCLK <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=20 ns
		CE <= transport '0';
		CLR <= transport '0';
		UP <= transport std_logic_vector'("00"); --0
		CCLK <= transport '1';
		-- --------------------
		WAIT FOR 20 ns; -- Time=40 ns
		CE <= transport '0';
		UP <= transport std_logic_vector'("00"); --0
		CCLK <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=60 ns
		UP <= transport std_logic_vector'("00"); --0
		CCLK <= transport '1';
		-- --------------------
		WAIT FOR 20 ns; -- Time=80 ns
		UP <= transport std_logic_vector'("00"); --0
		CCLK <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=100 ns
		UP <= transport std_logic_vector'("00"); --0
		CCLK <= transport '1';
		-- --------------------
		WAIT FOR 20 ns; -- Time=120 ns
		UP <= transport std_logic_vector'("01"); --1
		CCLK <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=140 ns
		UP <= transport std_logic_vector'("01"); --1
		CCLK <= transport '1';
		-- --------------------
		WAIT FOR 20 ns; -- Time=160 ns
		UP <= transport std_logic_vector'("01"); --1
		CCLK <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=180 ns
		UP <= transport std_logic_vector'("01"); --1
		CCLK <= transport '1';
		-- --------------------
		WAIT FOR 20 ns; -- Time=200 ns
		UP <= transport std_logic_vector'("11"); --3
		CCLK <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=220 ns
		UP <= transport std_logic_vector'("11"); --3
		CCLK <= transport '1';
		-- --------------------
		WAIT FOR 20 ns; -- Time=240 ns
		UP <= transport std_logic_vector'("11"); --3
		-- --------------------
		WAIT FOR 20 ns; -- Time=260 ns
		UP <= transport std_logic_vector'("10"); --2
		-- --------------------
		WAIT FOR 20 ns; -- Time=280 ns
		UP <= transport std_logic_vector'("10"); --2
		CCLK <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=300 ns
		UP <= transport std_logic_vector'("10"); --2
		CCLK <= transport '1';
		-- --------------------
		WAIT FOR 20 ns; -- Time=320 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION count4_cfg OF countt1 IS
	FOR testbench_arch
	END FOR;
END count4_cfg;