?? selwave.vhw
字號:
-- D:\FPGA\XC_9572
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Tue Apr 25 16:03:09 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
-- - Save it as a file with a .vhd extension (i.e. File->Save As...)
-- - Add it to your project as a testbench source (i.e. Project->Add Source...)
--
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.NUMERIC_STD.ALL;USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY selwave IS
END selwave;
ARCHITECTURE testbench_arch OF selwave IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
COMPONENT sel4_1
PORT (
A0 : In std_logic;
A1 : In std_logic;
CS : In std_logic;
MR_0 : In std_logic_vector (7 DOWNTO 0);
MR_1 : In std_logic_vector (7 DOWNTO 0);
MR_2 : In std_logic_vector (7 DOWNTO 0);
MR_3 : In std_logic_vector (7 DOWNTO 0);
DO : Out std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
SIGNAL A0 : std_logic;
SIGNAL A1 : std_logic;
SIGNAL CS : std_logic;
SIGNAL MR_0 : std_logic_vector (7 DOWNTO 0);
SIGNAL MR_1 : std_logic_vector (7 DOWNTO 0);
SIGNAL MR_2 : std_logic_vector (7 DOWNTO 0);
SIGNAL MR_3 : std_logic_vector (7 DOWNTO 0);
SIGNAL DO : std_logic_vector (7 DOWNTO 0);
BEGIN
UUT : sel4_1
PORT MAP (
A0 => A0,
A1 => A1,
CS => CS,
MR_0 => MR_0,
MR_1 => MR_1,
MR_2 => MR_2,
MR_3 => MR_3,
DO => DO
);
PROCESS
VARIABLE TX_OUT : LINE;
VARIABLE TX_ERROR : INTEGER := 0;
PROCEDURE CHECK_DO(
next_DO : std_logic_vector (7 DOWNTO 0);
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (DO /= next_DO) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns DO="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DO);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_DO);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
BEGIN
-- --------------------
A0 <= transport '0';
A1 <= transport '0';
CS <= transport '1';
MR_0 <= transport std_logic_vector'("00000000"); --0
MR_1 <= transport std_logic_vector'("00000000"); --0
MR_2 <= transport std_logic_vector'("00000000"); --0
MR_3 <= transport std_logic_vector'("00000000"); --0
-- --------------------
WAIT FOR 100 ns; -- Time=100 ns
A0 <= transport '1';
MR_0 <= transport std_logic_vector'("00110111"); --37
MR_1 <= transport std_logic_vector'("01000010"); --42
MR_2 <= transport std_logic_vector'("01001101"); --4D
MR_3 <= transport std_logic_vector'("00100001"); --21
-- --------------------
WAIT FOR 100 ns; -- Time=200 ns
A0 <= transport '0';
A1 <= transport '1';
MR_0 <= transport std_logic_vector'("00110111"); --37
MR_1 <= transport std_logic_vector'("01000010"); --42
MR_2 <= transport std_logic_vector'("01001101"); --4D
MR_3 <= transport std_logic_vector'("00100001"); --21
-- --------------------
WAIT FOR 100 ns; -- Time=300 ns
A0 <= transport '1';
CS <= transport '0';
MR_0 <= transport std_logic_vector'("00110111"); --37
MR_1 <= transport std_logic_vector'("01000010"); --42
MR_2 <= transport std_logic_vector'("01001101"); --4D
MR_3 <= transport std_logic_vector'("00100001"); --21
-- --------------------
WAIT FOR 100 ns; -- Time=400 ns
A0 <= transport '0';
A1 <= transport '0';
MR_0 <= transport std_logic_vector'("00110111"); --37
MR_1 <= transport std_logic_vector'("01000010"); --42
MR_2 <= transport std_logic_vector'("01001101"); --4D
MR_3 <= transport std_logic_vector'("00100001"); --21
-- --------------------
WAIT FOR 100 ns; -- Time=500 ns
A0 <= transport '1';
MR_0 <= transport std_logic_vector'("00110111"); --37
MR_1 <= transport std_logic_vector'("01000010"); --42
MR_2 <= transport std_logic_vector'("01001101"); --4D
MR_3 <= transport std_logic_vector'("00100001"); --21
-- --------------------
WAIT FOR 100 ns; -- Time=600 ns
A0 <= transport '0';
A1 <= transport '1';
MR_0 <= transport std_logic_vector'("00110111"); --37
MR_1 <= transport std_logic_vector'("01000010"); --42
MR_2 <= transport std_logic_vector'("01001101"); --4D
MR_3 <= transport std_logic_vector'("00100001"); --21
-- --------------------
WAIT FOR 100 ns; -- Time=700 ns
A0 <= transport '1';
MR_0 <= transport std_logic_vector'("00110111"); --37
MR_1 <= transport std_logic_vector'("01000010"); --42
MR_2 <= transport std_logic_vector'("01001101"); --4D
MR_3 <= transport std_logic_vector'("00100001"); --21
-- --------------------
WAIT FOR 100 ns; -- Time=800 ns
A0 <= transport '0';
A1 <= transport '0';
MR_0 <= transport std_logic_vector'("00110111"); --37
MR_1 <= transport std_logic_vector'("01000010"); --42
MR_2 <= transport std_logic_vector'("01001101"); --4D
MR_3 <= transport std_logic_vector'("00100001"); --21
-- --------------------
WAIT FOR 100 ns; -- Time=900 ns
A0 <= transport '1';
MR_0 <= transport std_logic_vector'("00110111"); --37
MR_1 <= transport std_logic_vector'("01000010"); --42
MR_2 <= transport std_logic_vector'("01001101"); --4D
MR_3 <= transport std_logic_vector'("00100001"); --21
-- --------------------
WAIT FOR 100 ns; -- Time=1000 ns
A0 <= transport '0';
A1 <= transport '1';
CS <= transport '1';
MR_0 <= transport std_logic_vector'("00110111"); --37
MR_1 <= transport std_logic_vector'("01000010"); --42
MR_2 <= transport std_logic_vector'("01001101"); --4D
MR_3 <= transport std_logic_vector'("00100001"); --21
-- --------------------
WAIT FOR 100 ns; -- Time=1100 ns
A0 <= transport '1';
MR_0 <= transport std_logic_vector'("00110111"); --37
MR_1 <= transport std_logic_vector'("01000010"); --42
MR_2 <= transport std_logic_vector'("01001101"); --4D
MR_3 <= transport std_logic_vector'("00100001"); --21
-- --------------------
WAIT FOR 100 ns; -- Time=1200 ns
A0 <= transport '0';
A1 <= transport '0';
MR_0 <= transport std_logic_vector'("00110111"); --37
MR_1 <= transport std_logic_vector'("01000010"); --42
MR_2 <= transport std_logic_vector'("01001101"); --4D
-- --------------------
WAIT FOR 100 ns; -- Time=1300 ns
A0 <= transport '1';
-- --------------------
WAIT FOR 100 ns; -- Time=1400 ns
A0 <= transport '0';
A1 <= transport '1';
-- --------------------
WAIT FOR 100 ns; -- Time=1500 ns
A0 <= transport '1';
-- --------------------
WAIT FOR 450 ns; -- Time=1950 ns
-- --------------------
IF (TX_ERROR = 0) THEN
STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
STD.TEXTIO.writeline(results, TX_OUT);
ASSERT (FALSE) REPORT
"Simulation successful (not a failure). No problems detected. "
SEVERITY FAILURE;
ELSE
STD.TEXTIO.write(TX_OUT, TX_ERROR);
STD.TEXTIO.write(TX_OUT, string'(
" errors found in simulation"));
STD.TEXTIO.writeline(results, TX_OUT);
ASSERT (FALSE) REPORT
"Errors found during simulation"
SEVERITY FAILURE;
END IF;
END PROCESS;
END testbench_arch;
CONFIGURATION sel4_1_cfg OF selwave IS
FOR testbench_arch
END FOR;
END sel4_1_cfg;
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