Annotate[50,ALMR,0]
Annotate[50,CLK,1]
Annotate[50,CS1,1]
Annotate[50,INT0,0]
Annotate[50,M1CLR,0]
Annotate[50,M1PS,0]
Annotate[50,M1SG,0]
Annotate[50,M2CLR,0]
Annotate[50,M2PS,0]
Annotate[50,M2SG,0]
Annotate[50,PC1ON,0]
Annotate[50,PC2ON,0]
Annotate[50,REL0,0]
Annotate[50,SEN0,0]
Annotate[50,SEN1,0]
Annotate[50,SEN2,0]
Annotate[50,SPDA1,0]
Annotate[50,SPDB1,0]
Annotate[50,SPDB2,0]
Annotate[50,SPD2A,0]
Annotate[50,UART0,1]
Annotate[50,D,UUUUUUUU]
Annotate[150,ALMR,0]
Annotate[150,CLK,0]
Annotate[150,CS1,1]
Annotate[150,INT0,1]
Annotate[150,M1CLR,0]
Annotate[150,M1PS,0]
Annotate[150,M1SG,0]
Annotate[150,M2CLR,0]
Annotate[150,M2PS,0]
Annotate[150,M2SG,0]
Annotate[150,PC1ON,0]
Annotate[150,PC2ON,0]
Annotate[150,REL0,0]
Annotate[150,SEN0,0]
Annotate[150,SEN1,0]
Annotate[150,SEN2,0]
Annotate[150,SPDA1,0]
Annotate[150,SPDB1,0]
Annotate[150,SPDB2,0]
Annotate[150,SPD2A,0]
Annotate[150,UART0,1]
Annotate[150,D,10000000]
Annotate[250,ALMR,0]
Annotate[250,CLK,1]
Annotate[250,CS1,1]
Annotate[250,INT0,1]
Annotate[250,M1CLR,0]
Annotate[250,M1PS,0]
Annotate[250,M1SG,0]
Annotate[250,M2CLR,0]
Annotate[250,M2PS,0]
Annotate[250,M2SG,0]
Annotate[250,PC1ON,0]
Annotate[250,PC2ON,0]
Annotate[250,REL0,0]
Annotate[250,SEN0,1]
Annotate[250,SEN1,0]
Annotate[250,SEN2,0]
Annotate[250,SPDA1,0]
Annotate[250,SPDB1,0]
Annotate[250,SPDB2,0]
Annotate[250,SPD2A,0]
Annotate[250,UART0,1]
Annotate[250,D,10000000]
Annotate[350,ALMR,0]
Annotate[350,CLK,0]
Annotate[350,CS1,1]
Annotate[350,INT0,0]
Annotate[350,M1CLR,0]
Annotate[350,M1PS,0]
Annotate[350,M1SG,0]
Annotate[350,M2CLR,0]
Annotate[350,M2PS,0]
Annotate[350,M2SG,0]
Annotate[350,PC1ON,0]
Annotate[350,PC2ON,0]
Annotate[350,REL0,0]
Annotate[350,SEN0,1]
Annotate[350,SEN1,0]
Annotate[350,SEN2,0]
Annotate[350,SPDA1,0]
Annotate[350,SPDB1,0]
Annotate[350,SPDB2,0]
Annotate[350,SPD2A,0]
Annotate[350,UART0,1]
Annotate[350,D,10000011]
Annotate[450,ALMR,0]
Annotate[450,CLK,1]
Annotate[450,CS1,1]
Annotate[450,INT0,0]
Annotate[450,M1CLR,0]
Annotate[450,M1PS,0]
Annotate[450,M1SG,0]
Annotate[450,M2CLR,0]
Annotate[450,M2PS,0]
Annotate[450,M2SG,0]
Annotate[450,PC1ON,0]
Annotate[450,PC2ON,0]
Annotate[450,REL0,1]
Annotate[450,SEN0,1]
Annotate[450,SEN1,0]
Annotate[450,SEN2,0]
Annotate[450,SPDA1,0]
Annotate[450,SPDB1,0]
Annotate[450,SPDB2,0]
Annotate[450,SPD2A,0]
Annotate[450,UART0,1]
Annotate[450,D,10000011]
Annotate[550,ALMR,0]
Annotate[550,CLK,0]
Annotate[550,CS1,1]
Annotate[550,INT0,1]
Annotate[550,M1CLR,0]
Annotate[550,M1PS,0]
Annotate[550,M1SG,0]
Annotate[550,M2CLR,0]
Annotate[550,M2PS,0]
Annotate[550,M2SG,0]
Annotate[550,PC1ON,0]
Annotate[550,PC2ON,0]
Annotate[550,REL0,1]
Annotate[550,SEN0,1]
Annotate[550,SEN1,0]
Annotate[550,SEN2,0]
Annotate[550,SPDA1,0]
Annotate[550,SPDB1,0]
Annotate[550,SPDB2,0]
Annotate[550,SPD2A,0]
Annotate[550,UART0,1]
Annotate[550,D,10000100]
Annotate[650,ALMR,0]
Annotate[650,CLK,1]
Annotate[650,CS1,1]
Annotate[650,INT0,1]
Annotate[650,M1CLR,0]
Annotate[650,M1PS,0]
Annotate[650,M1SG,0]
Annotate[650,M2CLR,0]
Annotate[650,M2PS,0]
Annotate[650,M2SG,0]
Annotate[650,PC1ON,0]
Annotate[650,PC2ON,0]
Annotate[650,REL0,1]
Annotate[650,SEN0,1]
Annotate[650,SEN1,0]
Annotate[650,SEN2,0]
Annotate[650,SPDA1,0]
Annotate[650,SPDB1,0]
Annotate[650,SPDB2,0]
Annotate[650,SPD2A,0]
Annotate[650,UART0,1]
Annotate[650,D,10000100]
Annotate[750,ALMR,0]
Annotate[750,CLK,0]
Annotate[750,CS1,1]
Annotate[750,INT0,0]
Annotate[750,M1CLR,0]
Annotate[750,M1PS,0]
Annotate[750,M1SG,0]
Annotate[750,M2CLR,0]
Annotate[750,M2PS,0]
Annotate[750,M2SG,0]
Annotate[750,PC1ON,0]
Annotate[750,PC2ON,0]
Annotate[750,REL0,1]
Annotate[750,SEN0,1]
Annotate[750,SEN1,0]
Annotate[750,SEN2,0]
Annotate[750,SPDA1,0]
Annotate[750,SPDB1,0]
Annotate[750,SPDB2,0]
Annotate[750,SPD2A,0]
Annotate[750,UART0,1]
Annotate[750,D,00000000]
Annotate[850,ALMR,0]
Annotate[850,CLK,1]
Annotate[850,CS1,1]
Annotate[850,INT0,1]
Annotate[850,M1CLR,0]
Annotate[850,M1PS,0]
Annotate[850,M1SG,0]
Annotate[850,M2CLR,0]
Annotate[850,M2PS,0]
Annotate[850,M2SG,0]
Annotate[850,PC1ON,0]
Annotate[850,PC2ON,0]
Annotate[850,REL0,1]
Annotate[850,SEN0,0]
Annotate[850,SEN1,0]
Annotate[850,SEN2,0]
Annotate[850,SPDA1,0]
Annotate[850,SPDB1,0]
Annotate[850,SPDB2,0]
Annotate[850,SPD2A,0]
Annotate[850,UART0,1]
Annotate[850,D,00000000]
Annotate[950,ALMR,0]
Annotate[950,CLK,1]
Annotate[950,CS1,1]
Annotate[950,INT0,1]
Annotate[950,M1CLR,0]
Annotate[950,M1PS,0]
Annotate[950,M1SG,0]
Annotate[950,M2CLR,0]
Annotate[950,M2PS,0]
Annotate[950,M2SG,0]
Annotate[950,PC1ON,0]
Annotate[950,PC2ON,0]
Annotate[950,REL0,1]
Annotate[950,SEN0,0]
Annotate[950,SEN1,0]
Annotate[950,SEN2,0]
Annotate[950,SPDA1,0]
Annotate[950,SPDB1,0]
Annotate[950,SPDB2,0]
Annotate[950,SPD2A,0]
Annotate[950,UART0,1]
Annotate[950,D,00000011]
Annotate[1050,ALMR,0]
Annotate[1050,CLK,1]
Annotate[1050,CS1,1]
Annotate[1050,INT0,1]
Annotate[1050,M1CLR,0]
Annotate[1050,M1PS,0]
Annotate[1050,M1SG,0]
Annotate[1050,M2CLR,0]
Annotate[1050,M2PS,0]
Annotate[1050,M2SG,0]
Annotate[1050,PC1ON,0]
Annotate[1050,PC2ON,0]
Annotate[1050,REL0,0]
Annotate[1050,SEN0,0]
Annotate[1050,SEN1,0]
Annotate[1050,SEN2,0]
Annotate[1050,SPDA1,0]
Annotate[1050,SPDB1,0]
Annotate[1050,SPDB2,0]
Annotate[1050,SPD2A,0]
Annotate[1050,UART0,0]
Annotate[1050,D,00000011]
Annotate[1150,ALMR,0]
Annotate[1150,CLK,1]
Annotate[1150,CS1,1]
Annotate[1150,INT0,1]
Annotate[1150,M1CLR,0]
Annotate[1150,M1PS,0]
Annotate[1150,M1SG,0]
Annotate[1150,M2CLR,0]
Annotate[1150,M2PS,0]
Annotate[1150,M2SG,0]
Annotate[1150,PC1ON,0]
Annotate[1150,PC2ON,0]
Annotate[1150,REL0,0]
Annotate[1150,SEN0,0]
Annotate[1150,SEN1,0]
Annotate[1150,SEN2,0]
Annotate[1150,SPDA1,0]
Annotate[1150,SPDB1,0]
Annotate[1150,SPDB2,0]
Annotate[1150,SPD2A,0]
Annotate[1150,UART0,0]
Annotate[1150,D,00000010]
Annotate[1250,ALMR,0]
Annotate[1250,CLK,1]
Annotate[1250,CS1,1]
Annotate[1250,INT0,1]
Annotate[1250,M1CLR,0]
Annotate[1250,M1PS,0]
Annotate[1250,M1SG,0]
Annotate[1250,M2CLR,0]
Annotate[1250,M2PS,0]
Annotate[1250,M2SG,0]
Annotate[1250,PC1ON,0]
Annotate[1250,PC2ON,0]
Annotate[1250,REL0,0]
Annotate[1250,SEN0,0]
Annotate[1250,SEN1,0]
Annotate[1250,SEN2,0]
Annotate[1250,SPDA1,0]
Annotate[1250,SPDB1,0]
Annotate[1250,SPDB2,0]
Annotate[1250,SPD2A,0]
Annotate[1250,UART0,0]
Annotate[1250,D,00000010]
Annotate[1350,ALMR,0]
Annotate[1350,CLK,1]
Annotate[1350,CS1,1]
Annotate[1350,INT0,1]
Annotate[1350,M1CLR,0]
Annotate[1350,M1PS,0]
Annotate[1350,M1SG,0]
Annotate[1350,M2CLR,0]
Annotate[1350,M2PS,0]
Annotate[1350,M2SG,0]
Annotate[1350,PC1ON,0]
Annotate[1350,PC2ON,0]
Annotate[1350,REL0,0]
Annotate[1350,SEN0,0]
Annotate[1350,SEN1,0]
Annotate[1350,SEN2,0]
Annotate[1350,SPDA1,0]
Annotate[1350,SPDB1,0]
Annotate[1350,SPDB2,0]
Annotate[1350,SPD2A,0]
Annotate[1350,UART0,1]
Annotate[1350,D,00000001]
Annotate[1450,ALMR,0]
Annotate[1450,CLK,1]
Annotate[1450,CS1,1]
Annotate[1450,INT0,1]
Annotate[1450,M1CLR,0]
Annotate[1450,M1PS,0]
Annotate[1450,M1SG,0]
Annotate[1450,M2CLR,0]
Annotate[1450,M2PS,0]
Annotate[1450,M2SG,0]
Annotate[1450,PC1ON,0]
Annotate[1450,PC2ON,0]
Annotate[1450,REL0,0]
Annotate[1450,SEN0,0]
Annotate[1450,SEN1,0]
Annotate[1450,SEN2,0]
Annotate[1450,SPDA1,0]
Annotate[1450,SPDB1,0]
Annotate[1450,SPDB2,0]
Annotate[1450,SPD2A,0]
Annotate[1450,UART0,1]
Annotate[1450,D,00000001]
Annotate[1550,ALMR,0]
Annotate[1550,CLK,1]
Annotate[1550,CS1,1]
Annotate[1550,INT0,1]
Annotate[1550,M1CLR,0]
Annotate[1550,M1PS,0]
Annotate[1550,M1SG,0]
Annotate[1550,M2CLR,0]
Annotate[1550,M2PS,0]
Annotate[1550,M2SG,0]
Annotate[1550,PC1ON,0]
Annotate[1550,PC2ON,0]
Annotate[1550,REL0,0]
Annotate[1550,SEN0,0]
Annotate[1550,SEN1,0]
Annotate[1550,SEN2,0]
Annotate[1550,SPDA1,0]
Annotate[1550,SPDB1,0]
Annotate[1550,SPDB2,0]
Annotate[1550,SPD2A,0]
Annotate[1550,UART0,0]
Annotate[1550,D,00000001]
Annotate[1650,ALMR,0]
Annotate[1650,CLK,1]
Annotate[1650,CS1,1]
Annotate[1650,INT0,1]
Annotate[1650,M1CLR,0]
Annotate[1650,M1PS,0]
Annotate[1650,M1SG,0]
Annotate[1650,M2CLR,0]
Annotate[1650,M2PS,0]
Annotate[1650,M2SG,0]
Annotate[1650,PC1ON,0]
Annotate[1650,PC2ON,0]
Annotate[1650,REL0,0]
Annotate[1650,SEN0,0]
Annotate[1650,SEN1,0]
Annotate[1650,SEN2,0]
Annotate[1650,SPDA1,0]
Annotate[1650,SPDB1,0]
Annotate[1650,SPDB2,0]
Annotate[1650,SPD2A,0]
Annotate[1650,UART0,0]
Annotate[1650,D,00000001]
Annotate[1750,ALMR,0]
Annotate[1750,CLK,1]
Annotate[1750,CS1,1]
Annotate[1750,INT0,1]
Annotate[1750,M1CLR,0]
Annotate[1750,M1PS,0]
Annotate[1750,M1SG,0]
Annotate[1750,M2CLR,0]
Annotate[1750,M2PS,0]
Annotate[1750,M2SG,0]
Annotate[1750,PC1ON,0]
Annotate[1750,PC2ON,0]
Annotate[1750,REL0,0]
Annotate[1750,SEN0,0]
Annotate[1750,SEN1,0]
Annotate[1750,SEN2,0]
Annotate[1750,SPDA1,0]
Annotate[1750,SPDB1,0]
Annotate[1750,SPDB2,0]
Annotate[1750,SPD2A,0]
Annotate[1750,UART0,0]
Annotate[1750,D,00000001]
Annotate[1850,ALMR,0]
Annotate[1850,CLK,1]
Annotate[1850,CS1,1]
Annotate[1850,INT0,1]
Annotate[1850,M1CLR,0]
Annotate[1850,M1PS,0]
Annotate[1850,M1SG,0]
Annotate[1850,M2CLR,0]
Annotate[1850,M2PS,0]
Annotate[1850,M2SG,0]
Annotate[1850,PC1ON,0]
Annotate[1850,PC2ON,0]
Annotate[1850,REL0,0]
Annotate[1850,SEN0,0]
Annotate[1850,SEN1,0]
Annotate[1850,SEN2,0]
Annotate[1850,SPDA1,0]
Annotate[1850,SPDB1,0]
Annotate[1850,SPDB2,0]
Annotate[1850,SPD2A,0]
Annotate[1850,UART0,0]
Annotate[1850,D,00000001]
Annotate[1950,ALMR,0]
Annotate[1950,CLK,1]
Annotate[1950,CS1,1]
Annotate[1950,INT0,1]
Annotate[1950,M1CLR,0]
Annotate[1950,M1PS,0]
Annotate[1950,M1SG,0]
Annotate[1950,M2CLR,0]
Annotate[1950,M2PS,0]
Annotate[1950,M2SG,0]
Annotate[1950,PC1ON,0]
Annotate[1950,PC2ON,0]
Annotate[1950,REL0,0]
Annotate[1950,SEN0,0]
Annotate[1950,SEN1,0]
Annotate[1950,SEN2,0]
Annotate[1950,SPDA1,0]
Annotate[1950,SPDB1,0]
Annotate[1950,SPDB2,0]
Annotate[1950,SPD2A,0]
Annotate[1950,UART0,0]
Annotate[1950,D,00000001]
Annotate[2050,ALMR,0]
Annotate[2050,CLK,1]
Annotate[2050,CS1,1]
Annotate[2050,INT0,1]
Annotate[2050,M1CLR,0]
Annotate[2050,M1PS,0]
Annotate[2050,M1SG,0]
Annotate[2050,M2CLR,0]
Annotate[2050,M2PS,0]
Annotate[2050,M2SG,0]
Annotate[2050,PC1ON,0]
Annotate[2050,PC2ON,0]
Annotate[2050,REL0,0]
Annotate[2050,SEN0,0]
Annotate[2050,SEN1,0]
Annotate[2050,SEN2,0]
Annotate[2050,SPDA1,0]
Annotate[2050,SPDB1,0]
Annotate[2050,SPDB2,0]
Annotate[2050,SPD2A,0]
Annotate[2050,UART0,0]
Annotate[2050,D,00000001]
Annotate[2150,ALMR,0]
Annotate[2150,CLK,1]
Annotate[2150,CS1,1]
Annotate[2150,INT0,1]
Annotate[2150,M1CLR,0]
Annotate[2150,M1PS,0]
Annotate[2150,M1SG,0]
Annotate[2150,M2CLR,0]
Annotate[2150,M2PS,0]
Annotate[2150,M2SG,0]
Annotate[2150,PC1ON,0]
Annotate[2150,PC2ON,0]
Annotate[2150,REL0,0]
Annotate[2150,SEN0,0]
Annotate[2150,SEN1,0]
Annotate[2150,SEN2,0]
Annotate[2150,SPDA1,0]
Annotate[2150,SPDB1,0]
Annotate[2150,SPDB2,0]
Annotate[2150,SPD2A,0]
Annotate[2150,UART0,0]
Annotate[2150,D,00000001]
Annotate[2250,ALMR,0]
Annotate[2250,CLK,1]
Annotate[2250,CS1,1]
Annotate[2250,INT0,1]
Annotate[2250,M1CLR,0]
Annotate[2250,M1PS,0]
Annotate[2250,M1SG,0]
Annotate[2250,M2CLR,0]
Annotate[2250,M2PS,0]
Annotate[2250,M2SG,0]
Annotate[2250,PC1ON,0]
Annotate[2250,PC2ON,0]
Annotate[2250,REL0,0]
Annotate[2250,SEN0,0]
Annotate[2250,SEN1,0]
Annotate[2250,SEN2,0]
Annotate[2250,SPDA1,0]
Annotate[2250,SPDB1,0]
Annotate[2250,SPDB2,0]
Annotate[2250,SPD2A,0]
Annotate[2250,UART0,0]
Annotate[2250,D,00000001]
Annotate[2350,ALMR,0]
Annotate[2350,CLK,1]
Annotate[2350,CS1,1]
Annotate[2350,INT0,1]
Annotate[2350,M1CLR,0]
Annotate[2350,M1PS,0]
Annotate[2350,M1SG,0]
Annotate[2350,M2CLR,0]
Annotate[2350,M2PS,0]
Annotate[2350,M2SG,0]
Annotate[2350,PC1ON,0]
Annotate[2350,PC2ON,0]
Annotate[2350,REL0,0]
Annotate[2350,SEN0,0]
Annotate[2350,SEN1,0]
Annotate[2350,SEN2,0]
Annotate[2350,SPDA1,0]
Annotate[2350,SPDB1,0]
Annotate[2350,SPDB2,0]
Annotate[2350,SPD2A,0]
Annotate[2350,UART0,0]
Annotate[2350,D,00000001]
Annotate[2450,ALMR,0]
Annotate[2450,CLK,1]
Annotate[2450,CS1,1]
Annotate[2450,INT0,1]
Annotate[2450,M1CLR,0]
Annotate[2450,M1PS,0]
Annotate[2450,M1SG,0]
Annotate[2450,M2CLR,0]
Annotate[2450,M2PS,0]
Annotate[2450,M2SG,0]
Annotate[2450,PC1ON,0]
Annotate[2450,PC2ON,0]
Annotate[2450,REL0,0]
Annotate[2450,SEN0,0]
Annotate[2450,SEN1,0]
Annotate[2450,SEN2,0]
Annotate[2450,SPDA1,0]
Annotate[2450,SPDB1,0]
Annotate[2450,SPDB2,0]
Annotate[2450,SPD2A,0]
Annotate[2450,UART0,0]
Annotate[2450,D,00000001]
Total[]