?? d24wave.vhw
字號:
-- D:\FPGA\TEST\XC_9572
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Wed Apr 12 15:09:04 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
-- - Save it as a file with a .vhd extension (i.e. File->Save As...)
-- - Add it to your project as a testbench source (i.e. Project->Add Source...)
--
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.NUMERIC_STD.ALL;USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY d24wave IS
END d24wave;
ARCHITECTURE testbench_arch OF d24wave IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
COMPONENT dq24
PORT (
D : In std_logic;
Din : In std_logic_vector (23 DOWNTO 0);
REST : In std_logic;
WR : In std_logic;
DQ0 : Out std_logic;
DQ1 : Out std_logic;
DQ2 : Out std_logic;
DQ3 : Out std_logic;
DQ4 : Out std_logic;
DQ5 : Out std_logic;
DQ6 : Out std_logic;
DQ7 : Out std_logic;
DQ8 : Out std_logic;
DQ9 : Out std_logic;
DQ10 : Out std_logic;
DQ11 : Out std_logic;
DQ12 : Out std_logic;
DQ13 : Out std_logic;
DQ14 : Out std_logic;
DQ15 : Out std_logic;
DQ16 : Out std_logic;
DQ17 : Out std_logic;
DQ18 : Out std_logic;
DQ19 : Out std_logic;
DQ20 : Out std_logic;
DQ21 : Out std_logic;
DQ22 : Out std_logic;
DQ23 : Out std_logic
);
END COMPONENT;
SIGNAL D : std_logic;
SIGNAL Din : std_logic_vector (23 DOWNTO 0);
SIGNAL REST : std_logic;
SIGNAL WR : std_logic;
SIGNAL DQ0 : std_logic;
SIGNAL DQ1 : std_logic;
SIGNAL DQ2 : std_logic;
SIGNAL DQ3 : std_logic;
SIGNAL DQ4 : std_logic;
SIGNAL DQ5 : std_logic;
SIGNAL DQ6 : std_logic;
SIGNAL DQ7 : std_logic;
SIGNAL DQ8 : std_logic;
SIGNAL DQ9 : std_logic;
SIGNAL DQ10 : std_logic;
SIGNAL DQ11 : std_logic;
SIGNAL DQ12 : std_logic;
SIGNAL DQ13 : std_logic;
SIGNAL DQ14 : std_logic;
SIGNAL DQ15 : std_logic;
SIGNAL DQ16 : std_logic;
SIGNAL DQ17 : std_logic;
SIGNAL DQ18 : std_logic;
SIGNAL DQ19 : std_logic;
SIGNAL DQ20 : std_logic;
SIGNAL DQ21 : std_logic;
SIGNAL DQ22 : std_logic;
SIGNAL DQ23 : std_logic;
BEGIN
UUT : dq24
PORT MAP (
D => D,
Din => Din,
REST => REST,
WR => WR,
DQ0 => DQ0,
DQ1 => DQ1,
DQ2 => DQ2,
DQ3 => DQ3,
DQ4 => DQ4,
DQ5 => DQ5,
DQ6 => DQ6,
DQ7 => DQ7,
DQ8 => DQ8,
DQ9 => DQ9,
DQ10 => DQ10,
DQ11 => DQ11,
DQ12 => DQ12,
DQ13 => DQ13,
DQ14 => DQ14,
DQ15 => DQ15,
DQ16 => DQ16,
DQ17 => DQ17,
DQ18 => DQ18,
DQ19 => DQ19,
DQ20 => DQ20,
DQ21 => DQ21,
DQ23 => DQ23
);
PROCESS
VARIABLE TX_OUT : LINE;
VARIABLE TX_ERROR : INTEGER := 0;
PROCEDURE CHECK_DQ3(
next_DQ3 : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (DQ3 /= next_DQ3) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns DQ3="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DQ3);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_DQ3);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_DQ1(
next_DQ1 : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (DQ1 /= next_DQ1) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns DQ1="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DQ1);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_DQ1);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_DQ2(
next_DQ2 : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (DQ2 /= next_DQ2) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns DQ2="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DQ2);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_DQ2);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_DQ4(
next_DQ4 : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (DQ4 /= next_DQ4) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns DQ4="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DQ4);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_DQ4);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_DQ5(
next_DQ5 : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (DQ5 /= next_DQ5) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns DQ5="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DQ5);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_DQ5);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_DQ6(
next_DQ6 : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (DQ6 /= next_DQ6) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns DQ6="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DQ6);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_DQ6);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_DQ7(
next_DQ7 : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (DQ7 /= next_DQ7) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns DQ7="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DQ7);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_DQ7);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_DQ8(
next_DQ8 : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (DQ8 /= next_DQ8) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
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