library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DECODE is
   port ( A0 : in    std_logic; 
          A1 : in    std_logic; 
          A2 : in    std_logic; 
          E  : in    std_logic; 
          D0 : out   std_logic; 
          D1 : out   std_logic; 
          D2 : out   std_logic; 
          D3 : out   std_logic);

end DECODE;

architecture Behavioral of DECODE is
signal  addr: std_logic_vector (1 downto 0);
signal  Dout: std_logic_vector (3 downto 0);
begin
  addr<=A1 & A0;
  process(A2,addr,E) 
  begin
  if(E='1') then
    Dout<="1111";
  elsif(A2='1') then
    Dout<="0111";  
  else   
	 case addr  is
	  	 when  "00"=> Dout<="1110"; 
	    when  "01"=> Dout<="1101";
	    when  "10"=> Dout<="1011";
	    when others=> Dout<="1111";
	 end case; 
  end if;
  end  process;
 
 D0<=Dout(0);
 D1<=Dout(1);
 D2<=Dout(2);
 D3<=Dout(3);

end Behavioral;