?? decodewave.vhw
字號:
-- D:\FPGA\TEST\XC_9572
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Fri Apr 07 09:31:34 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
-- - Save it as a file with a .vhd extension (i.e. File->Save As...)
-- - Add it to your project as a testbench source (i.e. Project->Add Source...)
--
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY decodewave IS
END decodewave;
ARCHITECTURE testbench_arch OF decodewave IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
COMPONENT decode
PORT (
A0 : In std_logic;
A1 : In std_logic;
A2 : In std_logic;
E : In std_logic;
D0 : Out std_logic;
D1 : Out std_logic;
D2 : Out std_logic;
D3 : Out std_logic
);
END COMPONENT;
SIGNAL A0 : std_logic;
SIGNAL A1 : std_logic;
SIGNAL A2 : std_logic;
SIGNAL E : std_logic;
SIGNAL D0 : std_logic;
SIGNAL D1 : std_logic;
SIGNAL D2 : std_logic;
SIGNAL D3 : std_logic;
BEGIN
UUT : decode
PORT MAP (
A0 => A0,
A1 => A1,
A2 => A2,
E => E,
D0 => D0,
D1 => D1,
D2 => D2,
D3 => D3
);
PROCESS
VARIABLE TX_OUT : LINE;
VARIABLE TX_ERROR : INTEGER := 0;
PROCEDURE CHECK_D0(
next_D0 : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (D0 /= next_D0) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns D0="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, D0);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_D0);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_D1(
next_D1 : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (D1 /= next_D1) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns D1="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, D1);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_D1);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_D2(
next_D2 : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (D2 /= next_D2) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns D2="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, D2);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_D2);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_D3(
next_D3 : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (D3 /= next_D3) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns D3="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, D3);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_D3);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
BEGIN
-- --------------------
A0 <= transport '0';
A1 <= transport '0';
A2 <= transport '0';
E <= transport '1';
-- --------------------
WAIT FOR 50 ns; -- Time=50 ns
CHECK_D0('1',50);
CHECK_D1('1',50);
CHECK_D2('1',50);
CHECK_D3('1',50);
-- --------------------
WAIT FOR 50 ns; -- Time=100 ns
A0 <= transport '1';
-- --------------------
WAIT FOR 50 ns; -- Time=150 ns
CHECK_D0('1',150);
CHECK_D1('1',150);
CHECK_D2('1',150);
CHECK_D3('1',150);
-- --------------------
WAIT FOR 50 ns; -- Time=200 ns
A0 <= transport '1';
A1 <= transport '1';
E <= transport '1';
-- --------------------
WAIT FOR 50 ns; -- Time=250 ns
CHECK_D0('1',250);
CHECK_D1('1',250);
CHECK_D2('1',250);
CHECK_D3('1',250);
-- --------------------
WAIT FOR 50 ns; -- Time=300 ns
A0 <= transport '0';
A1 <= transport '0';
A2 <= transport '1';
-- --------------------
WAIT FOR 50 ns; -- Time=350 ns
CHECK_D0('1',350);
CHECK_D1('1',350);
CHECK_D2('1',350);
CHECK_D3('1',350);
-- --------------------
WAIT FOR 50 ns; -- Time=400 ns
A0 <= transport '1';
-- --------------------
WAIT FOR 50 ns; -- Time=450 ns
CHECK_D0('1',450);
CHECK_D1('1',450);
CHECK_D2('1',450);
CHECK_D3('1',450);
-- --------------------
WAIT FOR 50 ns; -- Time=500 ns
A1 <= transport '1';
-- --------------------
WAIT FOR 50 ns; -- Time=550 ns
CHECK_D0('1',550);
CHECK_D1('1',550);
CHECK_D2('1',550);
CHECK_D3('1',550);
-- --------------------
WAIT FOR 50 ns; -- Time=600 ns
A0 <= transport '0';
A1 <= transport '0';
A2 <= transport '0';
E <= transport '0';
-- --------------------
WAIT FOR 50 ns; -- Time=650 ns
CHECK_D0('0',650);
CHECK_D1('1',650);
CHECK_D2('1',650);
CHECK_D3('1',650);
-- --------------------
WAIT FOR 50 ns; -- Time=700 ns
A0 <= transport '1';
E <= transport '0';
-- --------------------
WAIT FOR 50 ns; -- Time=750 ns
CHECK_D0('1',750);
CHECK_D1('0',750);
CHECK_D2('1',750);
CHECK_D3('1',750);
-- --------------------
WAIT FOR 50 ns; -- Time=800 ns
A0 <= transport '0';
A1 <= transport '1';
-- --------------------
WAIT FOR 50 ns; -- Time=850 ns
CHECK_D0('1',850);
CHECK_D1('1',850);
CHECK_D2('0',850);
CHECK_D3('1',850);
-- --------------------
WAIT FOR 50 ns; -- Time=900 ns
A0 <= transport '1';
-- --------------------
WAIT FOR 50 ns; -- Time=950 ns
CHECK_D0('1',950);
CHECK_D1('1',950);
CHECK_D2('1',950);
CHECK_D3('1',950);
-- --------------------
WAIT FOR 50 ns; -- Time=1000 ns
A0 <= transport '0';
A1 <= transport '0';
A2 <= transport '1';
-- --------------------
WAIT FOR 50 ns; -- Time=1050 ns
CHECK_D0('1',1050);
CHECK_D1('1',1050);
CHECK_D2('1',1050);
CHECK_D3('0',1050);
-- --------------------
WAIT FOR 50 ns; -- Time=1100 ns
A0 <= transport '1';
-- --------------------
WAIT FOR 50 ns; -- Time=1150 ns
CHECK_D0('1',1150);
CHECK_D1('1',1150);
CHECK_D2('1',1150);
CHECK_D3('0',1150);
-- --------------------
WAIT FOR 50 ns; -- Time=1200 ns
A0 <= transport '0';
A1 <= transport '1';
-- --------------------
WAIT FOR 50 ns; -- Time=1250 ns
CHECK_D0('1',1250);
CHECK_D1('1',1250);
CHECK_D2('1',1250);
CHECK_D3('0',1250);
-- --------------------
WAIT FOR 50 ns; -- Time=1300 ns
A0 <= transport '1';
-- --------------------
WAIT FOR 50 ns; -- Time=1350 ns
CHECK_D0('1',1350);
CHECK_D1('1',1350);
CHECK_D2('1',1350);
CHECK_D3('0',1350);
-- --------------------
WAIT FOR 50 ns; -- Time=1400 ns
A0 <= transport '0';
A1 <= transport '0';
A2 <= transport '0';
E <= transport '1';
-- --------------------
WAIT FOR 50 ns; -- Time=1450 ns
CHECK_D0('1',1450);
CHECK_D1('1',1450);
CHECK_D2('1',1450);
CHECK_D3('1',1450);
-- --------------------
WAIT FOR 100 ns; -- Time=1550 ns
CHECK_D0('1',1550);
CHECK_D1('1',1550);
CHECK_D2('1',1550);
CHECK_D3('1',1550);
-- --------------------
WAIT FOR 50 ns; -- Time=1600 ns
-- --------------------
IF (TX_ERROR = 0) THEN
STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
STD.TEXTIO.writeline(results, TX_OUT);
ASSERT (FALSE) REPORT
"Simulation successful (not a failure). No problems detected. "
SEVERITY FAILURE;
ELSE
STD.TEXTIO.write(TX_OUT, TX_ERROR);
STD.TEXTIO.write(TX_OUT, string'(
" errors found in simulation"));
STD.TEXTIO.writeline(results, TX_OUT);
ASSERT (FALSE) REPORT
"Errors found during simulation"
SEVERITY FAILURE;
END IF;
END PROCESS;
END testbench_arch;
CONFIGURATION decode_cfg OF decodewave IS
FOR testbench_arch
END FOR;
END decode_cfg;
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