Release 6.3i - xst G.35Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.48 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.48 s | Elapsed : 0.00 / 0.00 s --> Reading design: logic.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis  5) Advanced HDL Synthesis     5.1) HDL Synthesis Report  6) Low Level Synthesis  7) Final Report=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : logic.prjInput Format                       : mixedIgnore Synthesis Constraint File   : NOVerilog Include Directory          : ---- Target ParametersOutput File Name                   : logicOutput Format                      : NGCTarget Device                      : xc9500---- Source OptionsTop Module Name                    : logicAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoMux Extraction                     : YESResource Sharing                   : YES---- Target OptionsAdd IO Buffers                     : YESEquivalent register Removal        : YESMACRO Preserve                     : YESXOR Preserve                       : YES---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : YESRTL Output                         : YesHierarchy Separator                : _Bus Delimiter                      : <>Case Specifier                     : maintain---- Other Optionslso                                : logic.lsoverilog2001                        : YESwysiwyg                            : NO==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file D:/FPGA/TEST/xc9572/logic.vhd in Library work.Architecture behavioral of Entity logic is up to date.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <logic> (Architecture <behavioral>).WARNING:Xst:819 - D:/FPGA/TEST/xc9572/logic.vhd line 53: The following signals are missing in the process sensitivity list:   ad2, M0UART, M1UART, M2UART.Entity <logic> analyzed. Unit <logic> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <logic>.    Related source file is D:/FPGA/TEST/xc9572/logic.vhd.Unit <logic> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <logic> ...=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : logic.ngrTop Level Output File Name         : logicOutput Format                      : NGCOptimization Goal                  : SpeedKeep Hierarchy                     : YESTarget Technology                  : xc9500Macro Preserve                     : YESXOR Preserve                       : YESwysiwyg                            : NODesign Statistics# IOs                              : 15Cell Usage :# BELS                             : 16#      AND2                        : 4#      INV                         : 5#      OR2                         : 6#      OR3                         : 1# IO Buffers                       : 15#      IBUF                        : 11#      OBUF                        : 4=========================================================================CPU : 1.28 / 2.13 s | Elapsed : 2.00 / 2.00 s --> Total memory usage is 50692 kilobytes