--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 6.3i
--  \   \         Application : 
--  /   /         Filename : testadd.vhf
-- /___/   /\     Timestamp : 04/05/2006 13:22:29
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: ADSU1_MXILINX_testadd
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity ADSU1_MXILINX_testadd is
   port ( ADD : in    std_logic; 
          A0  : in    std_logic; 
          B0  : in    std_logic; 
          CI  : in    std_logic; 
          CO  : out   std_logic; 
          S0  : out   std_logic);
end ADSU1_MXILINX_testadd;

architecture BEHAVIORAL of ADSU1_MXILINX_testadd is
   attribute BOX_TYPE   : string ;
   signal XLXN_7  : std_logic;
   signal XLXN_8  : std_logic;
   signal XLXN_9  : std_logic;
   signal XLXN_10 : std_logic;
   signal XLXN_11 : std_logic;
   signal XLXN_12 : std_logic;
   signal XLXN_13 : std_logic;
   signal XLXN_14 : std_logic;
   signal XLXN_15 : std_logic;
   signal XLXN_16 : std_logic;
   component AND3
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3 : component is "BLACK_BOX";
   
   component AND3B2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3B2 : component is "BLACK_BOX";
   
   component AND2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
   
   component OR5
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             I4 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR5 : component is "BLACK_BOX";
   
   component AND3B1
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX";
   
   component AND3B3
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3B3 : component is "BLACK_BOX";
   
   component OR4
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR4 : component is "BLACK_BOX";
   
   component XOR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of XOR2 : component is "BLACK_BOX";
   
begin
   I_36_38 : AND3
      port map (I0=>ADD,      
                I1=>B0,      
                I2=>A0,      
                O=>XLXN_16);
   
   I_36_39 : AND3
      port map (I0=>ADD,      
                I1=>B0,      
                I2=>CI,      
                O=>XLXN_15);
   
   I_36_40 : AND3B2
      port map (I0=>ADD,      
                I1=>B0,      
                I2=>A0,      
                O=>XLXN_14);
   
   I_36_41 : AND2
      port map (I0=>CI,      
                I1=>A0,      
                O=>XLXN_12);
   
   I_36_42 : OR5
      port map (I0=>XLXN_12,      
                I1=>XLXN_13,      
                I2=>XLXN_14,      
                I3=>XLXN_15,      
                I4=>XLXN_16,      
                O=>CO);
   
   I_36_107 : AND3B2
      port map (I0=>ADD,      
                I1=>B0,      
                I2=>CI,      
                O=>XLXN_13);
   
   I_36_125 : AND3B1
      port map (I0=>CI,      
                I1=>ADD,      
                I2=>B0,      
                O=>XLXN_7);
   
   I_36_127 : AND3B3
      port map (I0=>CI,      
                I1=>ADD,      
                I2=>B0,      
                O=>XLXN_9);
   
   I_36_128 : OR4
      port map (I0=>XLXN_10,      
                I1=>XLXN_8,      
                I2=>XLXN_7,      
                I3=>XLXN_9,      
                O=>XLXN_11);
   
   I_36_129 : XOR2
      port map (I0=>XLXN_11,      
                I1=>A0,      
                O=>S0);
   
   I_36_130 : AND3B1
      port map (I0=>B0,      
                I1=>ADD,      
                I2=>CI,      
                O=>XLXN_8);
   
   I_36_131 : AND3B1
      port map (I0=>ADD,      
                I1=>CI,      
                I2=>B0,      
                O=>XLXN_10);
   
end BEHAVIORAL;


--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 6.3i
--  \   \         Application : 
--  /   /         Filename : testadd.vhf
-- /___/   /\     Timestamp : 04/05/2006 13:22:29
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: testadd
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity testadd is
   port ( );
end testadd;

architecture BEHAVIORAL of testadd is
   attribute HU_SET     : string ;
   component ADSU1_MXILINX_testadd
      port ( A0  : in    std_logic; 
             ADD : in    std_logic; 
             B0  : in    std_logic; 
             CI  : in    std_logic; 
             CO  : out   std_logic; 
             S0  : out   std_logic);
   end component;
   
   attribute HU_SET of XLXI_1 : label is "XLXI_1_0";
begin
   XLXI_1 : ADSU1_MXILINX_testadd
      port map (ADD=>open,      
                A0=>open,      
                B0=>open,      
                CI=>open,      
                CO=>open,      
                S0=>open);
   
end BEHAVIORAL;