?? count_top.vhd
字號:
--頂層文件源代碼如下所示：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity count_top is
Port ( rst : in std_logic;
clkin : in std_logic;
ld : in std_logic;
up : in std_logic;
hs : out std_logic;
vs : out std_logic;
r : out std_logic_vector(2 downto 0);
g : out std_logic_vector(2 downto 0);
b : out std_logic_vector(1 downto 0));
end count_top;
architecture Behavioral of count_top is
component counter
port( CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
CE, LOAD, DIR: in STD_LOGIC;
DIN: in STD_LOGIC_VECTOR(15 downto 0);
COUNT: inout STD_LOGIC_VECTOR(15 downto 0));
end component;
component HEX2LED_4
Port ( HEX : in std_logic_vector(15 downto 0);
LED1 : out std_logic_vector(6 downto 0);
LED2 : out std_logic_vector(6 downto 0);
LED3 : out std_logic_vector(6 downto 0);
LED4 : out std_logic_vector(6 downto 0));
end component;
component vga_16
Port ( clk : in std_logic;
hs : out std_logic;
vs : out std_logic;
r : out std_logic;
g : out std_logic;
b : out std_logic;
innum : in std_logic_vector(15 downto 0);
innum0 : in std_logic_vector(15 downto 0);
innum1 : in std_logic_vector(6 downto 0);
innum2 : in std_logic_vector(6 downto 0);
innum3 : in std_logic_vector(6 downto 0);
innum4 : in std_logic_vector(6 downto 0));
end component;
signal clk: std_logic;
signal N: std_logic_vector(23 downto 0);
signal do: std_logic_vector(15 downto 0);
signal din: std_logic_vector(15 downto 0);
signal ce: std_logic;
signal vga_r,vga_g,vga_b: std_logic;
signal HEX : std_logic_vector(15 downto 0);
signal LED1 : std_logic_vector(6 downto 0);
signal LED2 : std_logic_vector(6 downto 0);
signal LED3 : std_logic_vector(6 downto 0);
signal LED4 : std_logic_vector(6 downto 0);
begin
process(clkin, N)
begin
if (clkin'event and clkin='1') then
N<=N+1;
end if;
end process;
clk<=N(23);
din<="0001001000110100";
ce<='1';
U1: counter port map(clk,rst,ce,ld,up,din,do);
U2: HEX2LED_4 port map(do, led1,led2,led3,led4);
U3:vga_16 port map(clkin,hs,vs,vga_r,vga_g,vga_b,do,do,led1,led2,led3,led4);
r(0) <= vga_r;
r(1) <= vga_r;
r(2) <= vga_r;
g(0) <= vga_g;
g(1) <= vga_g;
g(2) <= vga_g;
b(0) <= vga_b;
b(1) <= vga_b;
end Behavioral;
--計數器源程序如下所示：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port(CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
CE, LOAD, DIR: in STD_LOGIC;
DIN: in STD_LOGIC_VECTOR(15 downto 0);
COUNT: inout STD_LOGIC_VECTOR(15 downto 0));
end counter;
architecture Behavioral of counter is
begin
process (CLK, RESET)
begin
if RESET='0' then
COUNT <= (others=>'0');
elsif CLK='1' and CLK'event then
if CE='1' then
if LOAD='0' then
COUNT <= DIN;
else
if DIR='1' then
COUNT <= COUNT + 1;
else
COUNT <= COUNT - 1;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
--數碼管譯碼源程序：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HEX2LED_4 is
Port ( HEX : in std_logic_vector(15 downto 0);
LED1 : out std_logic_vector(6 downto 0);
LED2 : out std_logic_vector(6 downto 0);
LED3 : out std_logic_vector(6 downto 0);
LED4 : out std_logic_vector(6 downto 0));
end HEX2LED_4;
architecture Behavioral of HEX2LED_4 is
begin
--HEX-to-seven-segment decoder
-- HEX: in STD_LOGIC_VECTOR (3 downto 0);
-- LED: out STD_LOGIC_VECTOR (6 downto 0);
--
-- segment encoding
-- 0
-- ---
-- 5 | | 1
-- --- <- 6
-- 4 | | 2
-- ---
-- 3
with HEX(3 downto 0) SELect
LED1<= "1111001" when "0001", --1
"0100100" when "0010", --2
"0110000" when "0011", --3
"0011001" when "0100", --4
"0010010" when "0101", --5
"0000010" when "0110", --6
"1111000" when "0111", --7
"0000000" when "1000", --8
"0010000" when "1001", --9
"0001000" when "1010", --A
"0000011" when "1011", --b
"1000110" when "1100", --C
"0100001" when "1101", --d
"0000110" when "1110", --E
"0001110" when "1111", --F
"1000000" when others; --0
with HEX(7 downto 4) SELect
LED2<= "1111001" when "0001", --1
"0100100" when "0010", --2
"0110000" when "0011", --3
"0011001" when "0100", --4
"0010010" when "0101", --5
"0000010" when "0110", --6
"1111000" when "0111", --7
"0000000" when "1000", --8
"0010000" when "1001", --9
"0001000" when "1010", --A
"0000011" when "1011", --b
"1000110" when "1100", --C
"0100001" when "1101", --d
"0000110" when "1110", --E
"0001110" when "1111", --F
"1000000" when others; --0
with HEX(11 downto 8) SELect
LED3<= "1111001" when "0001", --1
"0100100" when "0010", --2
"0110000" when "0011", --3
"0011001" when "0100", --4
"0010010" when "0101", --5
"0000010" when "0110", --6
"1111000" when "0111", --7
"0000000" when "1000", --8
"0010000" when "1001", --9
"0001000" when "1010", --A
"0000011" when "1011", --b
"1000110" when "1100", --C
"0100001" when "1101", --d
"0000110" when "1110", --E
"0001110" when "1111", --F
"1000000" when others; --0
with HEX(15 downto 12) SELect
LED4<= "1111001" when "0001", --1
"0100100" when "0010", --2
"0110000" when "0011", --3
"0011001" when "0100", --4
"0010010" when "0101", --5
"0000010" when "0110", --6
"1111000" when "0111", --7
"0000000" when "1000", --8
"0010000" when "1001", --9
"0001000" when "1010", --A
"0000011" when "1011", --b
"1000110" when "1100", --C
"0100001" when "1101", --d
"0000110" when "1110", --E
"0001110" when "1111", --F
"1000000" when others; --0
end Behavioral;
--VGA顯示源程序：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_16 is
Port ( clk : in std_logic;
hs : out std_logic;
vs : out std_logic;
r : out std_logic;
g : out std_logic;
b : out std_logic;
innum : in std_logic_vector(15 downto 0);
innum0 : in std_logic_vector(15 downto 0);
innum1 : in std_logic_vector(6 downto 0);
innum2 : in std_logic_vector(6 downto 0);
innum3 : in std_logic_vector(6 downto 0);
innum4 : in std_logic_vector(6 downto 0));
end vga_16;
architecture Behavioral of vga_16 is
constant color1: std_logic_vector:="010"; --顯示顏色為紅色
constant color2: std_logic_vector:="100";
constant color3: std_logic_vector:="001";
constant color4: std_logic_vector:="110";
signal hs1,vs1,fclk,cclk: std_logic;
signal fs: std_logic_vector(5 downto 0);
signal cc: std_logic_vector(4 downto 0);
signal ll: std_logic_vector(8 downto 0);
signal rgbp: std_logic_vector(3 downto 1);
signal rgb: std_logic_vector(3 downto 1);
begin
rgb(1)<=rgbp(1) and hs1 and vs1;
rgb(2)<=rgbp(2) and hs1 and vs1;
rgb(3)<=rgbp(3) and hs1 and vs1;
fclk<=fs(5);
cclk<=cc(4);
hs<=hs1;
vs<=vs1;
r<=rgb(2);
g<=rgb(3);
b<=rgb(1);
process(clk)
begin
if clk'event and clk='1' then
if fs=50 then
fs<="000000";
else
fs<=fs+1;
end if;
end if;
end process;
process(fclk)
begin
if fclk'event and fclk='1' then
if cc=27 then
cc<="00000";
else
cc<=cc+1;
end if;
end if;
end process;
process(cclk)
begin
if cclk'event and cclk='1' then
if ll=481 then
ll<="000000000";
else
ll<=ll+1;
end if;
end if;
end process;
process(cc, ll)
begin
if cc>23 then --行同步
hs1<='0';
else hs1<='1';
end if;
if ll>479 then --場同步
vs1<='0';
else vs1<='1';
end if;
end process;
process(cc,ll,innum,innum0,innum1,innum2,innum3,innum4)
begin
if cc>2 and cc<7 then
if ll>60 and ll<101 and innum4(0)='0' then --a0
rgbp<=color1;
elsif ll>180 and ll<221 and innum4(6)='0' then --g0
rgbp<=color1;
elsif ll>300 and ll<341 and innum4(3)='0' then --d0
rgbp<=color1;
elsif ll>60 and ll<202 then
if (cc>2 and cc<4) and innum4(5)='0' then --f0
rgbp<=color1;
elsif (cc>5 and cc<7) and innum4(1)='0' then --b0
rgbp<=color1;
else rgbp<="000";
end if;
elsif ll>201 and ll<341 then
if (cc>2 and cc<4) and innum4(4)='0' then --e0
rgbp<=color1;
elsif (cc>5 and cc<7) and innum4(2)='0' then --c0
rgbp<=color1;
else rgbp<="000";
end if;
elsif ll>350 and ll<370 then
if cc>2 and cc<4 and innum(15)='1' then --p8
rgbp<=color1;
elsif cc>3 and cc<5 and innum(14)='1' then --p4
rgbp<=color1;
elsif cc>4 and cc<6 and innum(13)='1' then --p2
rgbp<=color1;
elsif cc>5 and cc<7 and innum(12)='1' then --p1
rgbp<=color1;
else rgbp<="000";
end if;
elsif ll>380 and ll<400 then
if cc>2 and cc<4 and innum0(15)='1' then --q8
rgbp<=color1;
elsif cc>3 and cc<5 and innum0(14)='1' then --q4
rgbp<=color1;
elsif cc>4 and cc<6 and innum0(13)='1' then --q2
rgbp<=color1;
elsif cc>5 and cc<7 and innum0(12)='1' then --q1
rgbp<=color1;
else rgbp<="000";
end if;
else
rgbp<="000";
end if;
elsif cc>7 and cc<12 then
if ll>60 and ll<101 and innum3(0)='0' then
rgbp<=color2;
elsif ll>180 and ll<221 and innum3(6)='0' then
rgbp<=color2;
elsif ll>300 and ll<341 and innum3(3)='0' then
rgbp<=color2;
elsif ll>60 and ll<202 then
if (cc>7 and cc<9) and innum3(5)='0' then
rgbp<=color2;
elsif (cc>10 and cc<12) and innum3(1)='0' then
rgbp<=color2;
else rgbp<="000";
end if;
elsif ll>201 and ll<341 then
if (cc>7 and cc<9) and innum3(4)='0' then
rgbp<=color2;
elsif (cc>10 and cc<12) and innum3(2)='0' then
rgbp<=color2;
else rgbp<="000";
end if;
elsif ll>350 and ll<370 then
if cc>7 and cc<9 and innum(11)='1' then
rgbp<=color2;
elsif cc>8 and cc<10 and innum(10)='1' then
rgbp<=color2;
elsif cc>9 and cc<11 and innum(9)='1' then
rgbp<=color2;
elsif cc>10 and cc<12 and innum(8)='1' then
rgbp<=color2;
else rgbp<="000";
end if;
elsif ll>380 and ll<400 then
if cc>7 and cc<9 and innum0(11)='1' then
rgbp<=color2;
elsif cc>8 and cc<10 and innum0(10)='1' then
rgbp<=color2;
elsif cc>9 and cc<11 and innum0(9)='1' then
rgbp<=color2;
elsif cc>10 and cc<12 and innum0(8)='1' then
rgbp<=color2;
else rgbp<="000";
end if;
else
rgbp<="000";
end if;
elsif cc>12 and cc<17 then
if ll>60 and ll<101 and innum2(0)='0' then
rgbp<=color3;
elsif ll>180 and ll<221 and innum2(6)='0' then
rgbp<=color3;
elsif ll>300 and ll<341 and innum2(3)='0' then
rgbp<=color3;
elsif ll>60 and ll<202 then
if (cc>12 and cc<14) and innum2(5)='0' then
rgbp<=color3;
elsif (cc>15 and cc<17) and innum2(1)='0' then
rgbp<=color3;
else rgbp<="000";
end if;
elsif ll>201 and ll<341 then
if (cc>12 and cc<14) and innum2(4)='0' then
rgbp<=color3;
elsif (cc>15 and cc<17) and innum2(2)='0' then
rgbp<=color3;
else rgbp<="000";
end if;
elsif ll>350 and ll<370 then
if cc>12 and cc<14 and innum(7)='1' then
rgbp<=color3;
elsif cc>13 and cc<15 and innum(6)='1' then
rgbp<=color3;
elsif cc>14 and cc<16 and innum(5)='1' then
rgbp<=color3;
elsif cc>15 and cc<17 and innum(4)='1' then
rgbp<=color3;
else rgbp<="000";
end if;
elsif ll>380 and ll<400 then
if cc>12 and cc<14 and innum0(7)='1' then
rgbp<=color3;
elsif cc>13 and cc<15 and innum0(6)='1' then
rgbp<=color3;
elsif cc>14 and cc<16 and innum0(5)='1' then
rgbp<=color3;
elsif cc>15 and cc<17 and innum0(4)='1' then
rgbp<=color3;
else rgbp<="000";
end if;
else
rgbp<="000";
end if;
elsif cc>17 and cc<22 then
if ll>60 and ll<101 and innum1(0)='0' then
rgbp<=color4;
elsif ll>180 and ll<221 and innum1(6)='0' then
rgbp<=color4;
elsif ll>300 and ll<341 and innum1(3)='0' then
rgbp<=color4;
elsif ll>60 and ll<202 then
if (cc>17 and cc<19) and innum1(5)='0' then
rgbp<=color4;
elsif (cc>20 and cc<22) and innum1(1)='0' then
rgbp<=color4;
else rgbp<="000";
end if;
elsif ll>201 and ll<341 then
if (cc>17 and cc<19) and innum1(4)='0' then
rgbp<=color4;
elsif (cc>20 and cc<22) and innum1(2)='0' then
rgbp<=color4;
else rgbp<="000";
end if;
elsif ll>350 and ll<370 then
if cc>17 and cc<19 and innum(3)='1' then
rgbp<=color4;
elsif cc>18 and cc<20 and innum(2)='1' then
rgbp<=color4;
elsif cc>19 and cc<21 and innum(1)='1' then
rgbp<=color4;
elsif cc>20 and cc<22 and innum(0)='1' then
rgbp<=color4;
else rgbp<="000";
end if;
elsif ll>380 and ll<400 then
if cc>17 and cc<19 and innum0(3)='1' then
rgbp<=color4;
elsif cc>18 and cc<20 and innum0(2)='1' then
rgbp<=color4;
elsif cc>19 and cc<21 and innum0(1)='1' then
rgbp<=color4;
elsif cc>20 and cc<22 and innum0(0)='1' then
rgbp<=color4;
else rgbp<="000";
end if;
else rgbp<="000";
end if;
else rgbp<="000";
end if;
end process;
end Behavioral;
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