?? 【dsp技術】-68013 slave fifo模代碼[威恒電子在線].htm
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<TD vAlign=top
align=middle><B>以文本方式查看主題</B><BR><BR>- <B>威恒電子在線</B> (http://www.vheng.com/bbs/index.asp)<BR>-- <B>【DSP技術】</B> (http://www.vheng.com/bbs/list.asp?boardid=5)<BR>---- <B>68013
Slave
FIFO模代碼</B> (http://www.vheng.com/bbs/dispbbs.asp?boardid=5&id=51)<BR>
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<TD vAlign=center
align=top>-- 作者：韋小寶<BR>-- 發布時間：2006-6-29
14:46:02<BR><B r>-- 68013 Slave FIFO模代碼<BR><FONT
size=2>TD_Init()<BR>{<BR>CPUCS = 0x10;
// CLKSPD[1:0]=10, for 48MHz operation<BR><BR>IFCONFIG = 0xc3;<BR>//
IFCLKSRC=1 , FIFOs executes on internal clk source<BR>// xMHz=1
, 48MHz internal clk rate<BR>// IFCLKOE=0 , tri state
IFCLK pin <BR>// IFCLKPOL=0 , Don\'t invert IFCLK pin signal from
internal clk<BR>// ASYNC=0 , master samples
synchronous<BR>// GSTATE=0 , Don\'t drive GPIF states out on
PORTE[2:0], debug WF<BR>// IFCFG[1:0]=11, FX2 in slave FIFO
mode<BR><BR><BR>SYNCDELAY; <BR>REVCTL = 0x03;
// use enhanced packet handling<BR><BR>// EP2 1024 BULK OUT
4x<BR>SYNCDELAY; <BR>EP2CFG =
0xA8; // EP2 if DIR = out ,TYPE = BULK, SIZE = 1024 ,BUF =
quad<BR><BR>// EP4 EP6 EP8 are not used in this
implementation...<BR>SYNCDELAY;
<BR>EP4CFG = 0x20; // clear valid
bit<BR>SYNCDELAY; <BR>EP6CFG = 0x60; //
clear valid bit<BR>SYNCDELAY; //
<BR>EP8CFG = 0x60; // clear valid
bit<BR><BR>SYNCDELAY; //
<BR>FIFORESET = 0x80; // activate NAK-ALL to
avoid race conditions<BR>SYNCDELAY;
// <BR>FIFORESET = 0x02; // reset, FIFO
2<BR>SYNCDELAY; // <BR>FIFORESET
= 0x04; // reset, FIFO 4<BR>SYNCDELAY;
// <BR>FIFORESET = 0x06;
// reset, FIFO 6<BR>SYNCDELAY;
// <BR>FIFORESET = 0x08; //
reset, FIFO 8<BR>SYNCDELAY; //
<BR>FIFORESET = 0x00; // deactivate
NAK-ALL<BR><BR>SYNCDELAY;<BR>// handle the case where we were already in
AUTO mode...<BR><BR>EP2FIFOCFG = 0x00; //
AUTOOUT=0, WORDWIDE=0<BR>SYNCDELAY;<BR><BR>EP2FIFOCFG = 0x11;
// AUTOOUT=1, WORDWIDE=1<BR>SYNCDELAY;<BR><BR>//
since the defaults are four times buffered we must write dummy byte counts
fourth<BR>SYNCDELAY; //
<BR>OUTPKTEND = 0x82; // arm first
buffer<BR>SYNCDELAY; //
<BR>OUTPKTEND = 0x82; // arm second
buffer<BR>SYNCDELAY; //
<BR>OUTPKTEND = 0x82; // arm third
buffer<BR>SYNCDELAY; //
<BR>OUTPKTEND = 0x82; // arm fourth
buffer<BR><BR>IFCONFIG |= 0x20; // drive IFCLK
pin signal at 48MHz<BR><BR><BR>Rwuen = TRUE;
// Enable remote-wakeup<BR>}<BR><BR>可是我發現這樣不行，控制面板不能向端點2寫入數據，顯示“Write
IOCTL failed"，好像沒有使能arm端點，于是我將程序改寫成這樣<BR>TD_Init()<BR>{<BR>CPUCS = 0x10;
<BR><BR>IFCONFIG = 0xc3;<BR><BR>SYNCDELAY;
<BR>REVCTL = 0x01; //注意，我設成自動arm
端點buffer模式<BR><BR> SYNCDELAY;
<BR>EP2CFG = 0xA8; <BR><BR>SYNCDELAY;
<BR>EP4CFG = 0x20;
<BR>SYNCDELAY; <BR>EP6CFG = 0x60;
<BR>SYNCDELAY; <BR>EP8CFG
= 0x60; <BR><BR>SYNCDELAY;
<BR>FIFORESET = 0x80;
<BR>SYNCDELAY;
<BR>FIFORESET = 0x02; <BR>SYNCDELAY;
<BR>FIFORESET = 0x04;
<BR>SYNCDELAY;
<BR>FIFORESET = 0x06; <BR>SYNCDELAY;
<BR>FIFORESET = 0x08;
<BR>SYNCDELAY;
<BR>FIFORESET = 0x00;
<BR><BR>SYNCDELAY;<BR><BR>EP2FIFOCFG = 0x00;
<BR>SYNCDELAY;<BR><BR>EP2FIFOCFG = 0x11; //自動arm端點2FIFO
<BR>SYNCDELAY;<BR>
<BR>IFCONFIG |= 0x20;
<BR><BR>Rwuen = TRUE;
<BR>}</FONT><BR><BR>
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