module isa(sa,sd,bclk,aen,bale,io16,iorc,iowc,iochkrdy ,drq1,dack1);		parameter io_reg0_addr='h300;	parameter io_reg1_addr='h302;		input aen;	input [11:0] sa;	inout [15:0] sd;	input bclk;	input bale;		input io16;	input iorc;	input iowc;	output iochkrdy;	output drq1;	input dack1;		reg drq1;	reg [11:0] addr;	reg [15:0] sd_send_buff;		reg [15:0] io_reg0,io_reg1,io_reg2;	reg [3:0] counter,sd_receive_point;	reg sd_send;	reg io16_reg;		reg iorc_reg;	reg iowc_reg;	wire chip_sel;		tri [15:0] sd=sd_send?sd_send_buff:16'bz;	assign chip_sel=(addr>=io_reg0_addr)&&(addr<=io_reg1_addr+1);	assign iochkrdy=1;		always @(negedge bale)	begin		if(!aen)		begin			addr<=sa;			if(counter==7) addr<='bx;		end	end	always @(posedge bclk)	begin		if(!aen)		begin			if(bale)			begin				counter<=0;			end			else if(counter==10)			begin				counter<=10;			end			else			begin				counter<=counter+1;			end		end	end	always @(negedge bclk)	begin		if( (counter==1)&&(chip_sel) )		begin			io16_reg<=io16;			iorc_reg<=iorc;			iowc_reg<=iowc;		end	end	always @(posedge bclk)	begin		if(!(io16_reg))			sd_receive_point<=1;		else			sd_receive_point<=4;	end		always @(posedge bclk)	begin		if( (counter==sd_receive_point)&&(chip_sel)&&(!(iowc)) )		begin			if(addr==io_reg0_addr)			io_reg0[7:0]<=sd[7:0];  			if(addr==(io_reg0_addr+1))	    io_reg0[15:8]<=sd[7:0];			if(addr==io_reg1_addr)			io_reg1[7:0]<=sd[7:0];  			if(addr==(io_reg1_addr+1))	    io_reg1[15:8]<=sd[7:0];					end	end	always @(posedge bclk)	begin		if( (!(iorc_reg))&&(chip_sel)&&((counter==5)||(counter==1)||(counter==2)||(counter==3)||(counter==4)) )		begin			sd_send<=1;			if(addr==io_reg0_addr)				sd_send_buff[7:0]<=io_reg0[7:0];			if(addr==(io_reg0_addr+1))			begin				sd_send_buff[15:8]<=io_reg0[15:8];				sd_send_buff[7:0]<=io_reg0[15:8];			end			if(addr==io_reg1_addr)				sd_send_buff[7:0]<=io_reg1[7:0];			if(addr==(io_reg1_addr+1))			begin				sd_send_buff[15:8]<=io_reg1[15:8];				sd_send_buff[7:0]<=io_reg1[15:8]; 			end		end		else		begin			sd_send<=0;		end	end	always @(io_reg0 or dack1)	begin		if(!dack1)			drq1<=0;		else if(io_reg0==8'h81)			drq1<=1;	endendmodule