end BCD4_7;

architecture behave of BCD4_7 is
	--signal ou: std_logic_vector (1 downto 0);
	--signal a: std_logic_vector (2 downto 0);
begin
	process(a)
	begin
	case a is
		--when"00"=>y<="0001";
		--when"01"=>y<="0010";
		--when"10"=>y<="0100";
		--when"11"=>y<="1000";
		--when others =>y<="ZZZZ";
		when"0000"=>y<="0111111";
		when"0001"=>y<="0000110";
		when"0010"=>y<="1011011";
		when"0011"=>y<="1001111";
		when"0100"=>y<="1100110";
		when"0101"=>y<="1101101";
		when"0110"=>y<="1111101";
		when"0111"=>y<="0100111";
		when"1000"=>y<="1111111";
		when"1001"=>y<="1101111";
		when"1010"=>y<="1110111";
		when"1100"=>y<="0111001";
		when"1101"=>y<="1011110";
		when"1110"=>y<="1111001";
		when others =>y<="ZZZZZZZ";
end case;
end process;
--y0<=y(0);
--y1<=y(1);
--y2<=y(2);
--y3<=y(3);
end behave;