library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity b60add is
	port(clk,ld,r:in std_logic;
		d:in std_logic_vector(5 downto 0);
		co:out std_logic;
		q:out std_logic_vector(5 downto 0));
end b60add;
architecture add of b60add is
begin
	process(clk,ld,r)
	variable tmp:std_logic_vector(5 downto 0);
	begin
		if r='1' then
			tmp:="000000";
			co<='0';
		elsif ld='0' then
			tmp:=d;
		elsif clk'event and clk='1'then
			if tmp="111011"then
				tmp:="000000";
				co<='1';
			else
				tmp:=tmp+1;
				co<='0';
			end if;
		end if;
		q<=tmp;
	end process;
end add;