library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity b60jian2 is
	port(clk,clear:in std_logic;
		--d:in std_logic_vector(5 downto 0);
		co:out std_logic;
		q:out std_logic_vector(5 downto 0));
end b60jian2;
architecture add of b60jian2 is
begin
	process(clk,clear)
	variable tmp:std_logic_vector(5 downto 0);
	begin
		if clear='1' then
			tmp:="111011";
			co<='0';
		elsif clk'event and clk='1'then
			if tmp="000000"then
				tmp:="111011";
				co<='1';
			else
				tmp:=tmp-1;
				co<='0';
			end if;
		end if;
		q<=tmp;
	end process;
end add;