CLASS altera_avalon_16_bit_vga
{
	ASSOCIATED_FILES 
	{
		Add_Program = "";
		Edit_Program = "";
		Generator_Program = "";
		Software_Rebuild_Program = "";
	}
	MODULE_DEFAULTS
	{
		class      = "altera_avalon_16_bit_vga";
		class_version = "2.0";
      HDL_INFO
      {
         Synthesis_HDL_Files = "image_package.vhd, vga_register_bank.vhd, line_buffer.vhd, vga_driver.vhd, image_dma.vhd, altera_avalon_16_bit_vga.vhd";
	   Simulation_HDL_Files = "image_package.vhd, vga_register_bank.vhd, line_buffer.vhd, vga_driver.vhd, image_dma.vhd, altera_avalon_16_bit_vga.vhd";
      }
      MASTER image_dma_master
		{
			SYSTEM_BUILDER_INFO 
			{
				Bus_Type = "avalon";
				Address_Width = "32";
				Data_Width = "32";
				Is_Enabled = "1";
				Interrupts_Enabled = "0";
			}
			PORT_WIRING 
			{
				PORT read_to_sram
				{
					type = "read";
					direction = "output";
					width = "1";
				}
				PORT address_to_sram
				{
					type = "address";
					direction = "output";
					width = "32";
				}
				PORT data_from_sram
				{
					type = "readdata";
					direction = "input";
					width = "32";
				}
				PORT waitrequest
				{
					type = "waitrequest";
					direction = "input";
					width = "1";
				}
				PORT readdatavalid
				{
					type = "readdatavalid";
					direction = "input";
					width = "1";
				}
			}
		}
	SLAVE config_slave
		{
	      SYSTEM_BUILDER_INFO 
	      {
		Bus_Type          = "avalon";
		Address_Width     = "3";
		Data_Width        = "32";
		Has_IRQ           = "1";
		Address_Alignment = "dynamic";
		Read_Wait_States  = "1";
		Write_Wait_States = "0";
	      }
			PORT_WIRING 
			{
			      PORT clk
               		{
                 			width = "1";
                  		direction = "input";
                 		 	type = "clk";
              	 	}
				PORT chipselect_config
				{
				      direction = "input";
				      type = "chipselect";
				      width = "1";
				}
				PORT address_config
				{
				      direction = "input";
				      is_shared = "1";
				      type = "address";
				      width = "3";
				}
				PORT read_config
				{
					type = "read";
					direction = "input";
					width = "1";
				}
				PORT readdata_config
				{
					type = "readdata";
					direction = "output";
					width = "32";
				}
				PORT write_config
				{
					type = "write";
					direction = "input";
					width = "1";
				}
				PORT writedata_config
				{
					type = "writedata";
					direction = "input";
					width = "32";
				}
				PORT irq
				{
					type = "irq";
					direction = "output";
					width = "1";
				}
			}
		}
		
		SYSTEM_BUILDER_INFO 
		{
			Instantiate_In_System_Module = "1";
			Is_Enabled = "1";
		}
		SIMULATION 
		{
		}
		PORT_WIRING 
		{
			PORT vga_clk
			{
				direction = "input";
				width = "1";
			}
			PORT clock25
			{
				direction = "input";
				width = "1";
			}
			PORT resetn
			{
				direction = "input";
				width = "1";
			}
			PORT vga_clock_external
			{
				direction = "output";
				width = "1";
			}
			PORT hsync
			{
				direction = "output";
				width = "1";
			}
			PORT vsync
			{
				direction = "output";
				width = "1";
			}
			PORT M1
			{
				direction = "output";
				width = "1";
			}
			PORT M2
			{
				direction = "output";
				width = "1";
			}
			PORT sync_n
			{
				direction = "output";
				width = "1";
			}
			PORT sync_t
			{
				direction = "output";
				width = "1";
			}
			PORT blank_n
			{
				direction = "output";
				width = "1";
			}			
			PORT R
			{
				direction = "output";
				width = "8";
			}
			PORT G
			{
				direction = "output";
				width = "8";
			}	
			PORT B
			{
				direction = "output";
				width = "8";
			}
		}
	}
	USER_INTERFACE
	{
		USER_LABELS
		{
			name="Altera Avalon 16-bit VGA Driver";
		technology = "Other";
		}
	}
	DEFAULT_GENERATOR
	{
		top_module_name = "altera_avalon_16_bit_vga";
		black_box = "0";
		synthesis_files = "image_package.vhd, vga_register_bank.vhd, line_buffer.vhd, image_dma.vhd, vga_driver.vhd, altera_avalon_16_bit_vga.vhd";
	}
}