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XAPP616.zip file contains 

The word document
Verilog files (*.v)
    huffman_en_full.v
Vhdl file (*.vhd)
    huffman_en_full.vhd


The Verilog and VHDL synthesized and places and routed using Foundation 5.1.03i.
Synplify ProVerilog was used for synthesis.