?? huffman_en_full.v
字號:
/**********************************************************************/
//scale factor --- how many bits ?
`timescale 1ns/1ps
module huffman_en (CLK, RST, rdy_in, rl_in, dc_in, scan_type, luma,
huffman_out, eob, rdy_out);
output [15:0] huffman_out;
output rdy_out;
input CLK, RST, eob;
input [11:0] dc_in;
input rdy_in, luma;
input scan_type; /* used to choose b/n intra(0) & non-intra(1)
blocks */
input[17:0] rl_in; /* run[5:0] + value[11:0] */
/* signals */
reg[6:0] cntr64;
reg rdy_out,cl_sum_rdy;
reg[3:0] size/* synthesis syn_romstyle = "select_rom" */;
reg[5:0] cl_sum, cl_sum_prev;
reg[15:0] huffman_out;
reg[3:0] codelength_dc /* synthesis syn_romstyle = "block_rom" */;
reg[4:0] codelength_ac,codelength1,codelength2;
reg[4:0] codelength_ac1;
reg[9:0] vlcode_dc /* synthesis syn_romstyle = "block_rom" */;
reg[17:0] vlcode1, vlcode2,vlcode3,vlcode4;
reg[17:0] vlcode_ac1,vlcode_ac;
reg[38:0] cl_sum_shift;
reg full_flag1,half_flag1,half_flag2,full_flag2,half_flag3,full_flag3;
reg full_flag4,half_flag4,full_flag5,full_flag6,half_flag5;
reg[38:0] mult_out;
reg[16:1] upper_reg1,middle_reg1,lower_reg1;
reg[16:1] upper_reg2, middle_reg2, middle_reg3;
/*****************************************************************************/
/* Find the size for the "Differential_DC" value. The differential_dc_size gives the number of
bits to be used to denote the DC_difference value. ram_dc_diff . Table 1 in document*/
always @ (posedge CLK)
begin
casex (dc_in)
12'b111111111111 : size = 4'd1;
12'b11111111110x : size = 4'd2;
12'b1111111110xx : size = 4'd3;
12'b111111110xxx : size = 4'd4;
12'b11111110xxxx : size = 4'd5;
12'b1111110xxxxx : size = 4'd6;
12'b111110xxxxxx : size = 4'd7;
12'b11110xxxxxxx : size = 4'd8;
12'b1110xxxxxxxx : size = 4'd9;
12'b110xxxxxxxxx : size = 4'd10;
12'b10xxxxxxxxxx : size = 4'd11;
12'b000000000000 : size = 4'd0;
12'b000000000001 : size = 4'd1;
12'b00000000001x : size = 4'd2;
12'b0000000001xx : size = 4'd3;
12'b000000001xxx : size = 4'd4;
12'b00000001xxxx : size = 4'd5;
12'b0000001xxxxx : size = 4'd6;
12'b000001xxxxxx : size = 4'd7;
12'b00001xxxxxxx : size = 4'd8;
12'b0001xxxxxxxx : size = 4'd9;
12'b001xxxxxxxxx : size = 4'd10;
12'b01xxxxxxxxxx : size = 4'd11;
default: size = 4'd0;
endcase
end
/*****************************************************************************/
/* variable length code and the corresponding code length for DC_Differential */
/* After finding the size of the DC_Differential, the variable length code used to denote it is found.
For example, if the size is 10, 10 bits are used to denote the dc_differential value and a variable
length code prefix of "111111110" is used along with the 10 bit value. */
/* luma = 1'b1 denotes a luminance block and lume = 1'b0 denotes a chrominance block */
always @ (posedge CLK)
begin
if (RST)
begin
vlcode_dc <= 10'b0; codelength_dc <= 4'd0;
end
else if (cntr64 == 1'b1)
begin
case (luma)
1'b1: begin
case (size) //ram_dc_size1
4'd0 : begin vlcode_dc <= 10'b0000000100; codelength_dc <= 4'd3; end
4'd1 : begin vlcode_dc <= 10'b0000000000; codelength_dc <= 4'd2; end
4'd2 : begin vlcode_dc <= 10'b0000000001; codelength_dc <= 4'd2; end
4'd3 : begin vlcode_dc <= 10'b0000000101; codelength_dc <= 4'd3; end
4'd4 : begin vlcode_dc <= 10'b0000000110; codelength_dc <= 4'd3; end
4'd5 : begin vlcode_dc <= 10'b0000001110; codelength_dc <= 4'd4; end
4'd6 : begin vlcode_dc <= 10'b0000011110; codelength_dc <= 4'd5; end
4'd7 : begin vlcode_dc <= 10'b0000111110; codelength_dc <= 4'd6; end
4'd8 : begin vlcode_dc <= 10'b0001111110; codelength_dc <= 4'd7; end
4'd9 : begin vlcode_dc <= 10'b0011111110; codelength_dc <= 4'd8; end
4'd10 : begin vlcode_dc <= 10'b0111111110; codelength_dc <= 4'd9; end
4'd11 : begin vlcode_dc <= 10'b0111111111; codelength_dc <= 4'd9; end
default: begin vlcode_dc <= 10'b0; codelength_dc <= 4'd0; end
endcase
end
//always @(size)
1'b0: begin
case (size) //ram_dc_size2
4'd0 : begin vlcode_dc <= 10'b0000000000; codelength_dc <= 4'd2; end
4'd1 : begin vlcode_dc <= 10'b0000000001; codelength_dc <= 4'd2; end
4'd2 : begin vlcode_dc <= 10'b0000000010; codelength_dc <= 4'd2; end
4'd3 : begin vlcode_dc <= 10'b0000000110; codelength_dc <= 4'd3; end
4'd4 : begin vlcode_dc <= 10'b0000001110; codelength_dc <= 4'd4; end
4'd5 : begin vlcode_dc <= 10'b0000011110; codelength_dc <= 4'd5; end
4'd6 : begin vlcode_dc <= 10'b0000111110; codelength_dc <= 4'd6; end
4'd7 : begin vlcode_dc <= 10'b0001111110; codelength_dc <= 4'd7; end
4'd8 : begin vlcode_dc <= 10'b0011111110; codelength_dc <= 4'd8; end
4'd9 : begin vlcode_dc <= 10'b0111111110; codelength_dc <= 4'd9; end
4'd10 : begin vlcode_dc <= 10'b1111111110; codelength_dc <= 4'd10; end
4'd11 : begin vlcode_dc <= 10'b1111111111; codelength_dc <= 4'd10; end
default: begin vlcode_dc <= 10'b0; codelength_dc <= 4'd0; end
endcase
end
endcase
end
end
/*****************************************************************************/
/* variable length code and corresponding code length for AC coefficients.
Table zero is used for intra blocks anf table one is used for non-intra
blocks. For a run/level pair not defined in table zero or one, an escape
code followed by a 6 bit run symbol and 12 bit level is used.*/
//assign run_level_pair <= {run_in,level_in};
/*always @ (posedge CLK)
begin
if (RST)
begin vlcode_ac1 <= {18'b0}; codelength_ac1 <= 5'd0; end
else
begin if (rdy_in == 1'b1)
begin
case(rl_in)
18'b000000000000000001:
begin vlcode_ac1 <= {17'b00000000000001010,rl_in[11]}; codelength_ac1 <= 5'd5; end
18'b000000000000000101:
begin vlcode_ac1 <= {17'b00000000000000111,rl_in[11]}; codelength_ac1 <= 5'd4; end
18'b000000000000001010:
begin vlcode_ac1 <= {17'b00000000000001110,rl_in[11]}; codelength_ac1 <= 5'd5; end
18'b000001000000000101:
begin vlcode_ac1 <= {18'b111100001111001101}; codelength_ac1 <= 5'd18; end
18'b000011000000000111:
begin vlcode_ac1 <= {17'b00000000000010111,rl_in[11]}; codelength_ac1 <= 5'd6; end
18'b000111000000001001:
begin vlcode_ac1 <= {17'b00000000000000000,rl_in[11]}; codelength_ac1 <= 5'd5; end
18'b010000000000010000:
begin vlcode_ac1 <= {17'b10000000000010110,rl_in[11]}; codelength_ac1 <= 5'd7; end
18'b010101000000001001:
begin vlcode_ac1 <= {17'b00000000000010110,rl_in[11]}; codelength_ac1 <= 5'd7; end
default:
begin vlcode_ac1 <= {18'b111111111111111111}; codelength_ac1 <= 5'd18; end
endcase
end
end
end*/
/*****************************************************************************/
always @ (posedge CLK)
if (RST)
begin vlcode_ac1 <= {18'b0}; codelength_ac1 <= 5'd0; end
else
begin
if (eob == 1'b1 && scan_type == 1'b1)
begin vlcode_ac1 <= 000000000000000010; codelength_ac1 <= 5'd2; end // NOTE 2
else if (eob == 1'b1 && scan_type == 1'b0)
begin vlcode_ac1 <= 000000000000000110; codelength_ac1 <= 5'd4; end // NOTE 2
else if (cntr64 == 7'b0000001 && ({rl_in[17:12],rl_in[10:0]}) == 17'b00000000000000001)
begin vlcode_ac1 <= {17'b00000000000000001,rl_in[11]};
codelength_ac1 <= 5'd2; end // note3, DC coeff
else
begin
/******************** scan type = x, run = x, level = 1 ********/
casex ({scan_type,rl_in[17:12],rl_in[10:0]})//(check)
{1'bx,6'bx,11'b00000000001}: // level = 1
begin
case({rl_in[17:12]}) //run
6'b010001: //17
begin vlcode_ac1 <= {17'b00000000000011111,rl_in[11]}; codelength_ac1 <= 5'd13; end
6'b010010: //18
begin vlcode_ac1 <= {17'b00000000000011010,rl_in[11]}; codelength_ac1 <= 5'd13; end
6'b010011: //19
begin vlcode_ac1 <= {17'b00000000000011001,rl_in[11]}; codelength_ac1 <= 5'd13; end
6'b010100: //20
begin vlcode_ac1 <= {17'b00000000000010111,rl_in[11]}; codelength_ac1 <= 5'd13; end
6'b010101: //21
begin vlcode_ac1 <= {17'b00000000000010110,rl_in[11]}; codelength_ac1 <= 5'd13; end
6'b010110: //22
begin vlcode_ac1 <= {17'b00000000000011111,rl_in[11]}; codelength_ac1 <= 5'd14; end
6'b010111: //23
begin vlcode_ac1 <= {17'b00000000000011110,rl_in[11]}; codelength_ac1 <= 5'd14; end
6'b011000: //24
begin vlcode_ac1 <= {17'b00000000000011101,rl_in[11]}; codelength_ac1 <= 5'd14; end
6'b011001: //25
begin vlcode_ac1 <= {17'b00000000000011100,rl_in[11]}; codelength_ac1 <= 5'd14; end
6'b011010: //26
begin vlcode_ac1 <= {17'b00000000000011011,rl_in[11]}; codelength_ac1 <= 5'd14; end
6'b011011: //27
begin vlcode_ac1 <= {17'b00000000000011111,rl_in[11]}; codelength_ac1 <= 5'd17; end
6'b011100: //28
begin vlcode_ac1 <= {17'b00000000000011110,rl_in[11]}; codelength_ac1 <= 5'd17; end
6'b011101: //29
begin vlcode_ac1 <= {17'b00000000000011101,rl_in[11]}; codelength_ac1 <= 5'd17; end
6'b011110: //30
begin vlcode_ac1 <= {17'b00000000000011100,rl_in[11]}; codelength_ac1 <= 5'd17; end
6'b011111: //31
begin vlcode_ac1 <= {17'b00000000000011011,rl_in[11]}; codelength_ac1 <= 5'd17; end
endcase
end
/******************** scan type = x, run = x, level = 2 ********/
{1'bx,6'bx,11'b00000000010}: //level = 2
begin
case({rl_in[17:12]}) //(run)
6'b000110: //6
begin vlcode_ac1 <= {17'b00000000000011110,rl_in[11]}; codelength_ac1 <= 5'd13; end
6'b000111: //7
begin vlcode_ac1 <= {17'b00000000000010101,rl_in[11]}; codelength_ac1 <= 5'd13; end
6'b001000: //8
begin vlcode_ac1 <= {17'b00000000000010001,rl_in[11]}; codelength_ac1 <= 5'd13; end
6'b001001: //9
begin vlcode_ac1 <= {17'b00000000000010001,rl_in[11]}; codelength_ac1 <= 5'd14; end
6'b001010: //10
begin vlcode_ac1 <= {17'b00000000000010000,rl_in[11]}; codelength_ac1 <= 5'd14; end
6'b001011: //11
begin vlcode_ac1 <= {17'b00000000000011010,rl_in[11]}; codelength_ac1 <= 5'd17; end
6'b001100: //12
begin vlcode_ac1 <= {17'b00000000000011001,rl_in[11]}; codelength_ac1 <= 5'd17; end
6'b001101: //13
begin vlcode_ac1 <= {17'b00000000000011000,rl_in[11]}; codelength_ac1 <= 5'd17; end
6'b001110: //14
begin vlcode_ac1 <= {17'b00000000000010111,rl_in[11]}; codelength_ac1 <= 5'd17; end
6'b001111: //15
begin vlcode_ac1 <= {17'b00000000000010110,rl_in[11]}; codelength_ac1 <= 5'd17; end
6'b010000: //16
begin vlcode_ac1 <= {17'b00000000000010101,rl_in[11]}; codelength_ac1 <= 5'd17; end
endcase
end
/******************** scan type = x, run = x, level = 3 ********/
{1'bx,6'bx,11'b00000000011}: //level = 3
begin
case ({rl_in[17:12]}) //(run)
6'b000011: //3
begin vlcode_ac1 <= {17'b00000000000011100,rl_in[11]}; codelength_ac1 <= 5'd13; end
6'b000100: //4
begin vlcode_ac1 <= {17'b00000000000010010,rl_in[11]}; codelength_ac1 <= 5'd13; end
6'b000101: //5
begin vlcode_ac1 <= {17'b00000000000010010,rl_in[11]}; codelength_ac1 <= 5'd14; end
6'b000110: //6
begin vlcode_ac1 <= {17'b00000000000010100,rl_in[11]}; codelength_ac1 <= 5'd17; end
endcase
end
/******************** scan type = x, run = 0, level = x ********/
{1'bx,6'b000000,11'bx}: //run = 0
begin
case ({1'b0,rl_in[10:0]}) //(level)
12'b000000010000: //16
begin vlcode_ac1 <= {17'b00000000000011111,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000010001: //17
begin vlcode_ac1 <= {17'b00000000000011110,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000010010: //18
begin vlcode_ac1 <= {17'b00000000000011101,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000010011: //19
begin vlcode_ac1 <= {17'b00000000000011100,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000010100: //20
begin vlcode_ac1 <= {17'b00000000000011011,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000010101: //21
begin vlcode_ac1 <= {17'b00000000000011010,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000010110: //22
begin vlcode_ac1 <= {17'b00000000000011001,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000010111: //23
begin vlcode_ac1 <= {17'b00000000000011000,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000011000: //24
begin vlcode_ac1 <= {17'b00000000000010111,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000011001: //25
begin vlcode_ac1 <= {17'b00000000000010110,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000011010: //26
begin vlcode_ac1 <= {17'b00000000000010101,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000011011: //27
begin vlcode_ac1 <= {17'b00000000000010100,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000011100: //28
begin vlcode_ac1 <= {17'b00000000000010011,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000011101: //29
begin vlcode_ac1 <= {17'b00000000000010010,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000011110: //30
begin vlcode_ac1 <= {17'b00000000000010001,rl_in[11]}; codelength_ac1 <= 5'd15; end
12'b000000011111: //31
begin vlcode_ac1 <= {17'b00000000000010000,rl_in[11]}; codelength_ac1 <= 5'd15; end
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