?? mul.v
字號:
`timescale 1ns/10ps
module mul(//input
clk,nrst,
a,b,mul_en,
//output
oen,product);
input clk,nrst;
input [7:0] a,b;
input mul_en;
output oen; //output enable
output [15:0] product;
reg [15:0] product;
reg [2:0] count;
wire load=(count==7);
wire oen =(count==0);
always@(posedge clk or negedge nrst)
begin
if (~nrst) count<= 3'b111;
else if (mul_en) count<= count-1;
end
wire [15:0] temp=(product<<1);
always@(posedge clk or negedge nrst)
begin
if (~nrst) product<= 0;
else if (mul_en)begin
if (~load) begin
if (b[count]) product<= temp+a;
else product<= temp;
end else if (load) begin
if (~b[7]) product<= 0;
else if (b[7]) product<= a;
end
end
end
endmodule
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