################################################################################# Pre Synthesis Script## This script only reads in the design and saves it in a DB file## Author: Rudolf Usselmann#         rudi@asics.ws## Revision:# 3/7/01 RU Initial Sript################################################################################## ==============================================# Setup Design Parameterssource ../bin/design_spec.dc# ==============================================# Setup Librariessource ../bin/lib_spec.dc# ==============================================# Setup File IOappend log_file ../log/$active_design "_pre.log"append pre_comp_db_file ../out/$design_name "_pre.db"sh rm -f $log_file# ==============================================# Setup Misc Variablesset hdlin_enable_vpp true       ;# Important - this enables 'ifdefs# ==============================================# Read Designecho "+++++++++ Analyzing all design files ..."         >> $log_fileforeach module $design_files {        echo "+++++++++ Reading: $module"               >> $log_file        echo +++++++++ Reading: $module        set module_file_name ""        append module_file_name $module ".v"        analyze -f verilog $module_file_name            >> $log_file        elaborate $module                               >> $log_file   }set current_design $active_designecho "+++++++++ Linking Design ..."                     >> $log_filelink >> $log_fileecho "+++++++++ Uniquifying Design ..."                 >> $log_fileuniquify >> $log_fileecho "+++++++++ Checking Design ..."                    >> $log_filecheck_design >> $log_file# ==============================================# Save Designecho "+++++++++ Saving Design ..."                      >> $log_filewrite_file -hierarchy -format db -output $pre_comp_db_file