entity testbench isend;-------------------------------------------------------------------------- testbench for 8-bit adder------------------------------------------------------------------------library IEEE;use IEEE.std_logic_1164.all;architecture decoder_3_8 of testbench is     component Decoder 	port (Dec_in    : in std_logic_vector(2 downto 0);          Dec_out		 : out std_logic_vector(7 downto 0));    end component;    signal Dec_in    : std_logic_vector(2 downto 0);    signal Dec_out		 : std_logic_vector(7 downto 0);        type test_record_t is record	Dec_in :  std_logic_vector(2 downto 0);	Dec_out :  std_logic_vector(7 downto 0);    end record;    type test_array_t is array(positive range <>) of test_record_t;    constant test_patterns : test_array_t := (	(Dec_in => "000", Dec_out => "11111110"),	(Dec_in => "001", Dec_out => "11111101"),	(Dec_in => "010", Dec_out => "11111011"),	(Dec_in => "011", Dec_out => "11110111"),	(Dec_in => "100", Dec_out => "11101111"),	(Dec_in => "101", Dec_out => "11011111"),	(Dec_in => "110", Dec_out => "10111111"),	(Dec_in => "111", Dec_out => "01111111")    );    --    -- convert a std_logic value to a character    --    type stdlogic_to_char_t is array(std_logic) of character;    constant to_char : stdlogic_to_char_t := (	'U' => 'U',	'X' => 'X',	'0' => '0',	'1' => '1',	'Z' => 'Z',	'W' => 'W',	'L' => 'L',	'H' => 'H',	'-' => '-');    --    -- convert a std_logic_vector to a string    --    function to_string(inp : std_logic_vector)    return string    is	alias vec : std_logic_vector(1 to inp'length) is inp;	variable result : string(vec'range);    begin	for i in vec'range loop	    result(i) := to_char(vec(i));	end loop;	return result;    end;begin    -- instantiate the component    uut: Decoder port map(Dec_in => Dec_in,			 Dec_out => Dec_out);     -- provide stimulus and check the result    test: process	variable vector : test_record_t;	variable found_error : boolean := false;    begin	for i in test_patterns'range loop	    vector := test_patterns(i);	    -- apply the stimuls	    Dec_in <= vector.Dec_in;	    -- wait for the outputs to settle	    wait for 100 ns;	    -- check the results	    if (Dec_out  /= vector.Dec_out) then		assert false		    report "Dec_out is " & to_string(Dec_out)		    & ". Expected " & to_string(vector.Dec_out);		found_error := true;	    end if;	end loop;	assert not found_error	  report "There were ERRORS in the test."	  severity note;	assert found_error	  report "Test completed with no errors."	  severity note;	wait;    end process;end;configuration test_decoder_behavioural of testbench is    for decoder_3_8	for all: Decoder 	    use entity work.Decoder(behavioural);	end for;    end for;end test_decoder_behavioural;configuration test_decoder_structural of testbench is    for decoder_3_8	for all: Decoder 	    use entity work.Decoder(Structural);	end for;    end for;end test_decoder_structural;