VGA圖象顯示控制器源程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bishe is
PORT (clk1:in std_logic;
hs1:out std_logic;
vs1:out std_logic;
dout1:out std_logic_vector(7 downto 0)
);
end bishe;
architecture behv of bishe is
COMPONENT view
PORT (clk:in std_logic;
hs:out std_logic;
vs:out std_logic;
dout:out std_logic_vector(7 downto 0);
mem_d:in std_logic_vector(7 downto 0);
mem_a:out std_logic_vector(16 downto 0); 
mem_rd:out std_logic;
mem_wr:out std_logic
);

END COMPONENT;

COMPONENT kb128rom
port (
address		: IN STD_LOGIC_VECTOR (16 DOWNTO 0);
		inclock: IN STD_LOGIC ;
		q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;

signal b: std_logic_vector(16 downto 0);
signal c: std_logic_vector(7 downto 0) ;

BEGIN
u_kb128rom : kb128rom port map(inclock=>clk1,address=>b,q=>c);
u_view :view port map(hs=>hs1,vs=>vs1,dout=>dout1,clk=>clk1,mem_a=>b,mem_d=>c);
END ARCHITECTURE behv;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity view is
port(clk:in std_logic;
hs:out std_logic;
vs:out std_logic;
dout:out std_logic_vector(7 downto 0);
mem_d:in std_logic_vector(7 downto 0);
mem_a:out std_logic_vector(16 downto 0); 
mem_rd:out std_logic;
mem_wr:out std_logic
);
end view;
architecture behv of view is
signal h_cnt:integer range 0 to 799;
signal v_cnt:integer range 0 to 524;
signal i_hs:std_logic;
signal i_vs:std_logic;
signal v_hs:std_logic;
signal v_vs:std_logic;
signal addr:std_logic_vector(16 downto 0);
BEGIN 

hs <= i_hs; 
vs <= i_vs; 

PROCESS(clk) 
BEGIN 
IF clk'EVENT AND clk = '1' THEN 
IF h_cnt = 799 THEN 
h_cnt <= 0; 
ELSE 
h_cnt <= h_cnt + 1; 
END IF; 
IF h_cnt = 96 THEN 
i_hs <= '1'; 
ELSIF h_cnt = 0 THEN 
i_hs <= '0'; 
END IF; 
IF h_cnt = 783 THEN 
v_hs <= '1'; 
ELSIF h_cnt = 144 THEN 
v_hs <= '0'; 
END IF; 
END IF; 
END PROCESS; 

PROCESS(i_hs) 
BEGIN 
IF i_hs'EVENT AND i_hs = '1' THEN 
IF v_cnt = 524 THEN 
v_cnt <= 0; 
ELSE 
v_cnt <= v_cnt + 1; 
END IF; 

IF v_cnt = 2 THEN 
i_vs <= '1'; 
ELSIF v_cnt = 0 THEN 
i_vs <= '0'; 
END IF; 
IF v_cnt = 514 THEN 
v_vs <= '1'; 
ELSIF v_cnt = 35 THEN 
v_vs <= '0'; 
END IF; 
END IF; 
END PROCESS; 

mem_a<=addr;
mem_rd<='0';
mem_wr<='1';
process(clk,v_hs,v_vs)
begin
if v_hs='1' then
addr(8 downto 0)<="000000000";
elsif clk'event and clk='1' then
addr(8 downto 0)<=addr(8 downto 0)+1;
end if;	
if(v_vs='1')or(v_hs='1') then
dout<="00000000";
elsif clk'event and clk='0' then
dout<=mem_d(7 downto 0);
end if;
end process;
process(i_hs,v_vs)
begin
if v_vs='1' then
addr(16 downto 9)<="00000000";
elsif i_hs'event and i_hs='1' then
addr(16 downto 9)<=addr(16 downto 9)+1;
end if;
end process;
end behv;



LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kb128rom IS
	PORT
	(address		: IN STD_LOGIC_VECTOR (16 DOWNTO 0);
		inclock		: IN STD_LOGIC ;
	q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END kb128rom;
ARCHITECTURE SYN OF kb128rom IS
	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
	COMPONENT lpm_rom
	GENERIC (
		lpm_width: NATURAL;
		lpm_widthad: NATURAL;
		lpm_address_control: STRING;
		lpm_outdata: STRING;
		lpm_file: STRING);
	PORT (
	address: IN STD_LOGIC_VECTOR (16 DOWNTO 0);
	inclock: IN STD_LOGIC ;
	q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
	END COMPONENT;
BEGIN
	q<= sub_wire0(7 DOWNTO 0);
lpm_rom_component : lpm_rom
	GENERIC MAP (
		LPM_WIDTH => 8,
	LPM_WIDTHAD => 17,
		LPM_ADDRESS_CONTROL => "REGISTERED",
		LPM_OUTDATA => "UNREGISTERED",
		LPM_FILE => " D:/lqf/tp.mif ")
	PORT MAP (
		address => address,
		inclock => inclock,
		q => sub_wire0);
END SYN;