-- Drawing number       : D10281-- Drawing description  : Viterbi decoder core---- Entity name          : d10281_acs-- Short description    : Add-Compare-Select unit-- Architecture(s)      : rtl---- Description          :-- -- The Add-Compare-Select (ACS) unit is based on modulo arithmetic, thus-- avoiding the need for any nasty "normalisation" maths.  Split out from-- d10281_sm, for faster synthesis.---- This code is based on extensive simulation with a 'C' model.  -- Only need this for the "+" function:LIBRARY ieee;USE     ieee.std_logic_arith.all;ARCHITECTURE rtl OF d10281_acs ISBEGIN  -- A single add-compare-select unit  add_comp_sel : PROCESS (bm_from_a, bm_from_b,                           sm_from_a, sm_from_b,                          y_from_a, y_from_b)    VARIABLE new_sm_from_a : state_metric_type;    VARIABLE new_sm_from_b : state_metric_type;  BEGIN    new_sm_from_a := unsigned(sm_from_a) + unsigned(bm_from_a);    new_sm_from_b := unsigned(sm_from_b) + unsigned(bm_from_b);    IF greater(new_sm_from_a, new_sm_from_b) THEN      next_sm   <= new_sm_from_b;      decision  <= '1';      out_y     <= y_from_b;    ELSE      next_sm   <= new_sm_from_a;      decision  <= '0';      out_y     <= y_from_a;    END IF;  END PROCESS add_comp_sel;  END rtl;