----------------------------------------------------------------------------- This VHDL file is generated by EASE/VHDL from TRANSLOGIC BV,-- the 'Entity Architecture Schematics Editor for VHDL' tool.---------------------------------------------------------------------------------------------------------------------------------------------------------- Architecture 'struct' of 'd10281'.----------------------------------------------------------------------------- Drawing number       : D10281-- Drawing description  : Viterbi decoder core-- -- ------------------------------------------------------------------- This ARCHICTURE is automatically generated by EASE - do not edit.-- -----------------------------------------------------------------ARCHITECTURE struct OF d10281 IS COMPONENT d10281_ts  PORT(    reset_n         : IN     std_logic ;    clk_ts          : IN     std_logic ;    field_sync      : IN     std_logic ;    viterbi_init    : IN     std_logic;    data_en         : IN     std_logic ;    data_in         : IN     std_logic_vector( INPUT_WIDTH-1 DOWNTO 0 ) ;    data_valid      : OUT    std_logic ;    data_out        : OUT    std_logic_vector( INPUT_WIDTH-1 DOWNTO 0 ) ;    trellis_sel     : OUT    std_logic_vector( 3 DOWNTO 0 ) ;    trellis_count   : OUT    std_logic_vector( 3 DOWNTO 0 )      ) ; END  COMPONENT ; COMPONENT d10281_bm  PORT(    xdata          : IN     std_logic_vector( INPUT_WIDTH-1 DOWNTO 0 ) ;    data_valid     : IN     std_logic;    trellis_sel_in : IN     std_logic_vector( 3 DOWNTO 0 ) ;    tre_count_in   : IN     std_logic_vector( 3 DOWNTO 0 ) ;    bm0            : OUT    branch_metric_type ;    bm1            : OUT    branch_metric_type ;    bm2            : OUT    branch_metric_type ;    bm3            : OUT    branch_metric_type ;    data_y         : OUT    std_logic_vector( 3 DOWNTO 0 );    clk_out        : IN     std_logic ;    clk_out_enable : OUT    std_logic ;    trellis_sel_out: OUT    std_logic_vector( 3 DOWNTO 0 ) ;    tre_count_out  : OUT    std_logic_vector( 3 DOWNTO 0 ) ;    reset_n        : IN     std_logic ;    viterbi_init   : IN     std_logic ) ; END COMPONENT ;  COMPONENT d10281_sm  PORT(    reset_n        : IN     std_logic ;    clk_out        : IN     std_logic ;    bm0            : IN     branch_metric_type ;    bm1            : IN     branch_metric_type ;    bm2            : IN     branch_metric_type ;    bm3            : IN     branch_metric_type ;    data_y         : IN     std_logic_vector( 3 DOWNTO 0 );    decision       : OUT    decision_vector_type ;    out_y          : OUT    std_logic_vector( trellis_width-1 DOWNTO 0 );    clk_out_enable : IN     std_logic ;    trellis_sel    : IN     std_logic_vector( 3 DOWNTO 0 );     viterbi_init   : IN     std_logic ) ; END COMPONENT ; COMPONENT d10281_ph  PORT(    reset_n        : IN     std_logic ;    clk_out        : IN     std_logic ;    decision       : IN     decision_vector_type ;    out_y          : IN     std_logic_vector( trellis_width-1 DOWNTO 0 );    dout           : OUT    std_logic_vector( 1 DOWNTO 0 ) ;    dovalid        : OUT    std_logic ;    trellis_index  : OUT    std_logic_vector( 3 DOWNTO 0 );    clk_out_enable : IN     std_logic ;    trellis_sel    : IN     std_logic_vector( 3 DOWNTO 0 );    trellis_count  : IN     std_logic_vector( 3 DOWNTO 0 );    mem_dout       : OUT    std_logic_vector( 2*trellis_width-1 DOWNTO 0 );    mem1_we_n      : OUT    std_logic ;    mem1_din       : IN     std_logic_vector( 2*trellis_width-1 DOWNTO 0 );    mem_cs_n       : OUT    std_logic ;    mem1_a         : OUT    std_logic_vector( traceback_addr_width+4-1 DOWNTO 0 ) ;    mem2_a         : OUT    std_logic_vector( traceback_addr_width+4-1 DOWNTO 0 ) ;    mem2_we_n      : OUT    std_logic ;    mem2_din       : IN     std_logic_vector( 2*trellis_width-1 DOWNTO 0 );    viterbi_init   : IN     std_logic     ) ; END COMPONENT ;  COMPONENT d10281_obf   PORT(    reset_n         : IN     std_logic ;    clk_obf         : IN     std_logic ;    viterbi_init    : IN     std_logic ;    data_en         : IN     std_logic ;    trellis_index   : IN     std_logic_vector( 3 DOWNTO 0 );    data_in         : IN     std_logic_vector( 1 DOWNTO 0 ) ;    data_valid      : OUT    std_logic ;    data_out        : OUT    std_logic_vector( 7 DOWNTO 0 ) ) ; END  COMPONENT ; SIGNAL ts_data           : std_logic_vector( INPUT_WIDTH-1 DOWNTO 0 ) ; SIGNAL ts_valid          : std_logic; SIGNAL decision          : decision_vector_type ; SIGNAL bm0               : branch_metric_type ; SIGNAL bm1               : branch_metric_type ; SIGNAL bm2               : branch_metric_type ; SIGNAL bm3               : branch_metric_type ; SIGNAL data_y            : std_logic_vector( 3 DOWNTO 0 ); SIGNAL out_y             : std_logic_vector( trellis_width-1 DOWNTO 0 ); SIGNAL clk_out_enable    : std_logic ; SIGNAL ph_data           : std_logic_vector( 1 DOWNTO 0 ); SIGNAL ph_valid          : std_logic; SIGNAL trellis_sel_ts    : std_logic_vector( 3 DOWNTO 0 ); SIGNAL trellis_count_ts  : std_logic_vector( 3 DOWNTO 0 ); SIGNAL trellis_sel       : std_logic_vector( 3 DOWNTO 0 ); SIGNAL trellis_count     : std_logic_vector( 3 DOWNTO 0 ); SIGNAL trellis_index     : std_logic_vector( 3 DOWNTO 0 );BEGIN-- TRELLIS SELECT-- BRANCH METRICS-- PATH HISTORY-- STATE METRICS-- OUTPUT BUFFER U_d10281_ts: d10281_ts   PORT MAP(    reset_n        => reset_n,    clk_ts         => clk,    field_sync     => field_sync,    viterbi_init   => viterbi_init,    data_en        => data_en,    data_in        => data_in,    data_valid     => ts_valid,    data_out       => ts_data,    trellis_sel    => trellis_sel_ts,    trellis_count  => trellis_count_ts        ) ; d10281_bm_1: d10281_bm    PORT MAP(      xdata => ts_data,      data_valid => ts_valid,      trellis_sel_in    => trellis_sel_ts,      tre_count_in  => trellis_count_ts,      bm0 => bm0,      bm1 => bm1,      bm2 => bm2,      bm3 => bm3,      clk_out => clk,      data_y  => data_y,      clk_out_enable => clk_out_enable,      trellis_sel_out    => trellis_sel,      tre_count_out     => trellis_count,      reset_n => reset_n,      viterbi_init => viterbi_init ) ; d10281_sm_1: d10281_sm    PORT MAP(      reset_n => reset_n,      clk_out => clk,      bm0 => bm0,      bm1 => bm1,      bm2 => bm2,      bm3 => bm3,      data_y   => data_y,      decision => decision,      out_y    => out_y,      clk_out_enable => clk_out_enable,      trellis_sel    => trellis_sel,       viterbi_init => viterbi_init ) ; d10281_ph_1: d10281_ph    PORT MAP(      reset_n => reset_n,      clk_out => clk,      decision => decision,      out_y    => out_y,      dout => ph_data,      dovalid => ph_valid,      trellis_index  => trellis_index,      clk_out_enable => clk_out_enable,      trellis_sel    => trellis_sel,      trellis_count     => trellis_count,      mem_dout => mem_dout,      mem1_we_n => mem1_we_n,      mem1_din => mem1_din,      mem_cs_n => mem_cs_n,      mem1_a => mem1_a,      mem2_a => mem2_a,      mem2_we_n => mem2_we_n,      mem2_din => mem2_din,      viterbi_init => viterbi_init       ) ;         U_d10281_obf: d10281_obf    PORT MAP(    reset_n         => reset_n,    clk_obf         => clk,    viterbi_init    => viterbi_init,    data_en         => ph_valid,    trellis_index   => trellis_index,    data_in         => ph_data,    data_valid      => data_valid,    data_out        => data_out ) ;END struct ; -- of d10281