-- Drawing number       : D10281-- Drawing description  : Viterbi decoder core---- Entity name          : D10281_TS-- Short description    : Trellis Select unit-- Architecture(s)      : RTL---- Description          :---- ARCHITECTURE rtl OF d10281_ts IS--==========================================-- Combinatorial signals--==========================================--==========================================-- Registers--==========================================  SIGNAL sym_count      : std_logic_vector( 9 DOWNTO 0 );  SIGNAL seg_count      : std_logic_vector( 1 DOWNTO 0 );  SIGNAL ts_count       : std_logic_vector( 3 DOWNTO 0 ) ;  SIGNAL ts_inc         : std_logic_vector( 3 DOWNTO 0 ) ;  SIGNAL seg_comp       : std_logic;  SIGNAL sym_comp       : std_logic;  SIGNAL sym_comp_d1    : std_logic;  SIGNAL ts_comp        : std_logic;  SIGNAL ts_inccomp     : std_logic;  SIGNAL data_valid_d1  : std_logic ;  SIGNAL data_out_d1    : std_logic_vector( INPUT_WIDTH-1 DOWNTO 0 ) ;  BEGIN   --===========================================================-- Combinatorial--===========================================================  sym_comp  <= '1' WHEN sym_count = "1100111011"  --828 symbol per segment               ELSE '0' ;    seg_comp  <= '1' WHEN seg_count = "10"  --3 segment               ELSE '0' ;                              ts_comp  <= '1' WHEN ts_count = "1011"  --12 trellis               ELSE '0' ;  ts_inccomp <= '1' WHEN ts_inc = "1011"  --12 trellis               ELSE '0' ;    trellis_sel  <= ts_count;  trellis_count   <= ts_inc ;                                               --===========================================================-- clock --===========================================================  sym_num : PROCESS (reset_n, clk_ts)  BEGIN    IF reset_n = '0' THEN        sym_count  <= "1100111011";    ELSIF clk_ts'EVENT AND clk_ts = '1' THEN      IF field_sync = '1' OR viterbi_init = '1' THEN        sym_count  <= "1100111011";      ELSIF data_en = '1' THEN        IF sym_comp = '1' THEN          sym_count  <= (OTHERS => '0');        ELSE          sym_count  <= unsigned(sym_count) + '1';        END IF;      END IF;    END IF;  END PROCESS sym_num;    seg_num : PROCESS (reset_n, clk_ts)  BEGIN    IF reset_n = '0' THEN        seg_count  <= "10";    ELSIF clk_ts'EVENT AND clk_ts = '1' THEN      IF field_sync = '1' OR viterbi_init = '1' THEN        seg_count  <= "10";      ELSIF sym_comp = '1' AND data_en = '1' THEN        IF seg_comp = '1' THEN          seg_count  <= (OTHERS => '0');        ELSE          seg_count  <= unsigned(seg_count) + '1';        END IF;              END IF;    END IF;  END PROCESS seg_num;     dvalid_d1 : PROCESS (reset_n, clk_ts)  BEGIN    IF reset_n = '0' THEN        data_valid_d1  <= '0';        data_out_d1    <= (OTHERS => '0');    ELSIF clk_ts'EVENT AND clk_ts = '1' THEN      IF field_sync = '1' OR viterbi_init = '1' THEN        data_valid_d1  <= '0';        data_out_d1    <= (OTHERS => '0');      ELSE        data_valid_d1  <= data_en;        data_out_d1    <= data_in;        END IF;         END IF;  END PROCESS dvalid_d1;        dvalid : PROCESS (reset_n, clk_ts)  BEGIN    IF reset_n = '0' THEN        data_valid  <= '0';        data_out    <= (OTHERS => '0');        sym_comp_d1 <= '0';    ELSIF clk_ts'EVENT AND clk_ts = '1' THEN      IF field_sync = '1' OR viterbi_init = '1' THEN        data_valid  <= '0';        data_out    <= (OTHERS => '0');        sym_comp_d1 <= '0';      ELSE        data_valid  <= data_valid_d1;        data_out    <= data_out_d1;        sym_comp_d1 <= sym_comp;      END IF;    END IF;  END PROCESS dvalid;       ts_num : PROCESS (reset_n, clk_ts)  BEGIN    IF reset_n = '0' THEN        ts_count  <= (OTHERS => '0');    ELSIF clk_ts'EVENT AND clk_ts = '1' THEN      IF field_sync = '1' OR viterbi_init = '1' THEN        ts_count  <= (OTHERS => '0');      ELSIF data_valid_d1 = '1' THEN        IF sym_comp_d1 = '1' THEN          ts_count  <= seg_count & "00";        ELSIF ts_comp = '1' THEN          ts_count  <= (OTHERS => '0');        ELSE          ts_count  <= unsigned(ts_count) + '1';        END IF;      END IF;    END IF;  END PROCESS ts_num;     ts_inc_pro : PROCESS (reset_n, clk_ts)  BEGIN    IF reset_n = '0' THEN        ts_inc  <= (OTHERS => '0');    ELSIF clk_ts'EVENT AND clk_ts = '1' THEN      IF field_sync = '1' OR viterbi_init = '1' THEN        ts_inc  <= (OTHERS => '0');      ELSIF data_valid_d1 = '1' THEN        IF sym_comp_d1 = '1' THEN          ts_inc  <= (OTHERS => '0');        ELSIF ts_inccomp = '1' THEN          ts_inc  <= (OTHERS => '0');        ELSE          ts_inc  <= unsigned(ts_inc) + '1';        END IF;      END IF;    END IF;  END PROCESS ts_inc_pro;   END rtl ;